Patents by Inventor Kazunari Kushiyama
Kazunari Kushiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9220137Abstract: A driver circuit is provided which comprises a series-connected unit having a light-emitting element and a current limiting inductor directly connected to the light-emitting element, a regenerative diode which is connected in parallel to the series-connected unit and which regenerates energy stored in the current limiting inductor, a transistor which controls a current flowing through the light-emitting element and the current limiting inductor, and a controller which controls an operation of the transistor, wherein the controller controls the transistor according to a voltage value of a power supply applied to the light-emitting element.Type: GrantFiled: March 2, 2014Date of Patent: December 22, 2015Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Yoshio Fujimura, Hiroshi Iizuka, Kazunari Kushiyama, Koudai Nakamura, Yuusuke Nishizaki, Kenpei En
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Publication number: 20140175994Abstract: A driver circuit is provided which comprises a series-connected unit having a light-emitting element and a current limiting inductor directly connected to the light-emitting element, a regenerative diode which is connected in parallel to the series-connected unit and which regenerates energy stored in the current limiting inductor, a transistor which controls a current flowing through the light-emitting element and the current limiting inductor, and a controller which controls an operation of the transistor, wherein the controller controls the transistor according to a voltage value of a power supply applied to the light-emitting element.Type: ApplicationFiled: March 2, 2014Publication date: June 26, 2014Applicant: Semiconductor Components Industries, LLCInventors: Yoshio Fujimura, Hiroshi Iizuka, Kazunari Kushiyama, Koudai Nakamura, Yuusuke Nishizaki, Kenpei En
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Patent number: 8665922Abstract: A driver circuit is provided which comprises a series-connected unit having a light-emitting element and a current limiting inductor directly connected to the light-emitting element, a regenerative diode which is connected in parallel to the series-connected unit and which regenerates energy stored in the current limiting inductor, a transistor which controls a current flowing through the light-emitting element and the current limiting inductor, and a controller which controls an operation of the transistor, wherein the controller controls the transistor according to a voltage value of a power supply applied to the light-emitting element.Type: GrantFiled: October 28, 2009Date of Patent: March 4, 2014Assignees: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.Inventors: Yoshio Fujimura, Hiroshi Iizuka, Kazunari Kushiyama, Koudai Nakamura, Yuusuke Nishizaki, Kenpei En
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Patent number: 8133788Abstract: An n type impurity region is provided below a gate electrode. By setting a gate length to be less than a depth of a channel region, a side surface of the channel region and a side surface of the n type impurity region adjacent to the channel region form a substantially perpendicular junction surface. Thus, since a depletion layer widens uniformly in a depth direction of a substrate, it is possible to secure a predetermined breakdown voltage. Furthermore, since an interval between the channel regions, above which the gate electrode is disposed, is uniform from its surface to its bottom, it is possible to increase an impurity concentration of the n type impurity region, resulting in an achievement of a low on-resistance.Type: GrantFiled: September 25, 2009Date of Patent: March 13, 2012Assignee: Semiconductor Components Industries, LLCInventors: Yasuyuki Sayama, Tetsuya Okada, Makoto Oikawa, Hiroyasu Ishida, Kazunari Kushiyama
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Publication number: 20100111123Abstract: A driver circuit is provided which comprises a series-connected unit having a light-emitting element and a current limiting inductor directly connected to the light-emitting element, a regenerative diode which is connected in parallel to the series-connected unit and which regenerates energy stored in the current limiting inductor, a transistor which controls a current flowing through the light-emitting element and the current limiting inductor, and a controller which controls an operation of the transistor, wherein the controller controls the transistor according to a voltage value of a power supply applied to the light-emitting element.Type: ApplicationFiled: October 28, 2009Publication date: May 6, 2010Applicants: SANYO ELECTRIC CO., LTD., SANYO SEMICONDUCTOR CO., LTD.Inventors: Yoshio Fujimura, Hiroshi Iizuka, Kazunari Kushiyama, Koudai Nakamura, Yuusuke Nishizaki, Kenpei En
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Publication number: 20100015772Abstract: An n type impurity region is provided below a gate electrode. By setting a gate length to be less than a depth of a channel region, a side surface of the channel region and a side surface of the n type impurity region adjacent to the channel region form a substantially perpendicular junction surface. Thus, since a depletion layer widens uniformly in a depth direction of a substrate, it is possible to secure a predetermined breakdown voltage. Furthermore, since an interval between the channel regions, above which the gate electrode is disposed, is uniform from its surface to its bottom, it is possible to increase an impurity concentration of the n type impurity region, resulting in an achievement of a low on-resistance.Type: ApplicationFiled: September 25, 2009Publication date: January 21, 2010Applicant: SANYO Electric Co., Ltd.Inventors: Yasuyuki SAYAMA, Tetsuya Okada, Makoto Oikawa, Hiroyasu Ishida, Kazunari Kushiyama
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Patent number: 7417295Abstract: Two metal electrode layers are provided. A first electrode layer is patterned with a minute separation distance according to an element region as in the case of the conventional case. Meanwhile, it suffices that a second electrode layer be in contact with the first electrode layer. Thus, no problems arise even if the separation distance is elongated. Specifically, the second electrode layer can be set to have a desired thickness. Moreover, by disposing a nitride film on the first electrode layer below a wire bonding region, even when volume expansion is caused by an Au/Al eutectic layer, transmission of stress to the element region can be prevented.Type: GrantFiled: August 1, 2006Date of Patent: August 26, 2008Assignee: Sanyo Electric Co., Ltd.Inventors: Kazunari Kushiyama, Tetsuya Okada, Makoto Oikawa
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Publication number: 20070072352Abstract: A separation hole is provided in the center of the gate electrode. Accordingly, it is possible to suppress a drastic increase in feedback capacitance Crss in the case where drain-source voltage VDS is decreased and the width of the depletion layer is narrowed. Thus, high-frequency switching characteristics are improved. Moreover, n type impurities are implanted from the separation hole to form an n type impurity region between channel regions. Since a resistance in a portion below the gate electrode can be reduced, an on-resistance can be reduced. The n type impurity region can be formed in a self-aligning manner.Type: ApplicationFiled: September 12, 2006Publication date: March 29, 2007Applicant: SANYO ELECTRIC CO., LTD.Inventors: Kazunari Kushiyama, Tetsuya Okada, Makoto Oikawa, Hiroyasu Ishida, Yasuyuki Sayama
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Publication number: 20070034943Abstract: Two metal electrode layers are provided. A first electrode layer is patterned with a minute separation distance according to an element region as in the case of the conventional case. Meanwhile, it suffices that a second electrode layer be in contact with the first electrode layer. Thus, no problems arise even if the separation distance is elongated. Specifically, the second electrode layer can be set to have a desired thickness. Moreover, by disposing a nitride film on the first electrode layer below a wire bonding region, even when volume expansion is caused by an Au/Al eutectic layer, transmission of stress to the element region can be prevented.Type: ApplicationFiled: August 1, 2006Publication date: February 15, 2007Applicant: SANYO ELECTRIC CO., LTD.Inventors: Kazunari Kushiyama, Tetsuya Okada, Makoto Oikawa
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Publication number: 20060220122Abstract: An n type impurity region is provided below a gate electrode. By setting a gate length to be less than a depth of a channel region, a side surface of the channel region and a side surface of the n type impurity region adjacent to the channel region form a substantially perpendicular junction surface. Thus, since a depletion layer widens uniformly in a depth direction of a substrate, it is possible to secure a predetermined breakdown voltage. Furthermore, since an interval between the channel regions, above which the gate electrode is disposed, is uniform from its surface to its bottom, it is possible to increase an impurity concentration of the n type impurity region, resulting in an achievement of a low on-resistance.Type: ApplicationFiled: March 13, 2006Publication date: October 5, 2006Applicant: SANYO ELECTRIC CO., LTD.Inventors: Yasuyuki Sayama, Tetsuya Okada, Makoto Oikawa, Hiroyasu Ishida, Kazunari Kushiyama
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Publication number: 20060180836Abstract: In the present invention, in a pattern in which gate electrodes are provided in a stripe shape and source regions are provided in a ladder shape, body regions are provided in a stripe shape parallel to the gate electrodes. A first body region is exposed to a surface of a channel layer between first source regions adjacent to the gate electrode, and a second body region is provided below a second source region which connects the first source regions to each other. Thus, avalanche resistance can be improved. Moreover, since a mask for forming the body region is no longer required, there is a margin in accuracy of alignment.Type: ApplicationFiled: February 16, 2006Publication date: August 17, 2006Applicant: SANYO ELECTRIC CO., LTD.Inventors: Hiroyasu Ishida, Makoto Oikawa, Kikuo Okada, Shouji Miyahara, Naohiro Ochiai, Kazunari Kushiyama