Abstract: A semiconductor device includes JTAG ports receiving integrally command information representing a command and password information representing a password, a processor for performing a process in response to the command, an output port outputting consequence information representing a consequence of the process, a transfer section for transferring the command to the processor and for transferring the consequence information to the output port, and a cut off section. The cutoff section cuts off at least one of transferring the command information to the processor and transferring the consequence information to the output port when the password does not match a predetermined proper password. Thus, the semiconductor device can advantageously heighten its security effect.

Abstract: A semiconductor device includes JTAG ports receiving integrally command information representing a command and password information representing a password, a processor for performing a process in response to the command, an output port outputting consequence information representing a consequence of the process, a transfer section for transferring the command to the processor and for transferring the consequence information to the output port, and a cut off section. The cutoff section cuts off at least one of transferring the command information to the processor and transferring the consequence information to the output port when the password does not match a predetermined proper password. Thus, the semiconductor device can advantageously heighten its security effect.

Abstract: A system LSI is provided which has a function of enabling data of an external device to be correctly read, when high-speed testing is carried out at a clock signal which is higher-speed than that at a time of usual operation. The system LSI has an external terminal for input of a wait signal from a testing device which is connected when high-speed testing is carried out. Moreover, when the wait signal is supplied to an external bus controller, the external bus controller extends an access time to a ROM during a period of time over which the wait signal is supplied.

Abstract: A memory controller which can freely set parameters without a significant increase in circuit scale. Selection information and addition information applied from a CPU as a data signal are held in a register. The selection information is commonly applied to a plurality of selectors as a selection signal, while the addition information is commonly applied to a plurality of adders as an addition value VA. Each of the selectors selects one from a plurality of input data in accordance with the select signal. The addition value is added to data output from the respective selectors in adders associated therewith, and the state machine is applied with the values of the addition results as parameters, i.e., an address setup value, an assert pulse width, and a data off value, respectively.

Abstract: A system LSI is provided which has a function of enabling data of an external device to be correctly read, when high-speed testing is carried out at a clock signal which is higher-speed than that at a time of usual operation. The system LSI has an external terminal for input of a wait signal from a testing device which is connected when high-speed testing is carried out. Moreover, when the wait signal is supplied to an external bus controller, the external bus controller extends an access time to a ROM during a period of time over which the wait signal is supplied.

Abstract: An interruption signal generating apparatus comprises a counter unit counting a predetermined time interval and outputting a count-up signal indicating the end of the counting; a first generating unit detecting the end of the counting indicated by the count-up signal and generating a first interruption signal indicating the detection according to a first clock; a second generating unit detecting the end of the counting indicated by the count-up signal and generating a second interruption signal indicating the detection according to a second clock; and a selecting unit selectively outputting the first and second interruption signals. Even in the stop mode in which a bus clock for making the computer system operative is unprovided, the interruption signal can be generated in a manner similar to the normal mode in which the bus clock is provided.

Abstract: An interruption signal generating apparatus comprises a counter unit counting a predetermined time interval and outputting a count-up signal indicating the end of the counting; a first generating unit detecting the end of the counting indicated by the count-up signal and generating a first interruption signal indicating the detection according to a first clock; a second generating unit detecting the end of the counting indicated by the count-up signal and generating a second interruption signal indicating the detection according to a second clock; and a selecting unit selectively outputting the first and second interruption signals. Even in the stop mode in which a bus clock for making the computer system operative is unprovided, the interruption signal can be generated in a manner similar to the normal mode in which the bus clock is provided.