Patents by Inventor Kazunari Shiota
Kazunari Shiota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10800967Abstract: Provided is a ceramic composition capable of achieving a light scattering function while maintaining optical properties at a high level. The ceramic composition comprises a fluorescence phase comprising a fluorescent material and a light-scattering phase comprising a lanthanum oxide. The lanthanum oxide may be, for example, at least one selected from LaAlO3 and La2O3. The ratio of the fluorescent material (or the fluorescence phase) to the lanthanum oxide (or the light-scattering phase), the former/the latter, may be 99.9/0.1 to 50/50 in terms of volume ratio.Type: GrantFiled: December 5, 2017Date of Patent: October 13, 2020Assignee: Konoshima Chemical Co., Ltd.Inventors: Takagimi Yanagitani, Katsuhiro Muramatsu, Atsuko Endo, Kazunari Shiota
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Publication number: 20200063029Abstract: Provided is a ceramic composition capable of achieving a light scattering function while maintaining optical properties at a high level. The ceramic composition comprises a fluorescence phase comprising a fluorescent material and a light-scattering phase comprising a lanthanum oxide. The lanthanum oxide may be, for example, at least one selected from LaAlO3 and La2O3. The ratio of the fluorescent material (or the fluorescence phase) to the lanthanum oxide (or the light-scattering phase), the former/the latter, may be 99.9/0.1 to 50/50 in terms of volume ratio.Type: ApplicationFiled: December 5, 2017Publication date: February 27, 2020Inventors: Takagimi Yanagitani, Katsuhiro Muramatsu, Atsuko Endo, Kazunari Shiota
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Patent number: 9215011Abstract: An optical receiver, includes: a signal processor to perform digital signal processing on a polarization demultiplexed signal obtained by demultiplexing a polarization multiplexed signal corresponding to a reception signal, the signal processor includes: an adaptive equalization circuit to compensate for the polarization demultiplexed signal by control of a filter coefficient; a first frequency offset estimation circuit to receive a first polarization demultiplexed signal diverged at a preceding stage and estimate a first frequency offset; a second frequency offset estimation circuit to receive a second polarization demultiplexed signal diverged at a succeeding stage and estimate a second frequency offset; and a decision circuit to decide whether the filter coefficient is correct based on a first difference between the first frequency offset and the second frequency offset and output, when deciding that the filter coefficient is incorrect, a first trigger for re-calculation of the filter coefficient.Type: GrantFiled: October 6, 2014Date of Patent: December 15, 2015Assignee: FUJITSU LIMITEDInventors: Kiichi Sugitani, Kazunari Shiota, Eri Katayama
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Publication number: 20150125150Abstract: An optical receiver, includes: a signal processor to perform digital signal processing on a polarization demultiplexed signal obtained by demultiplexing a polarization multiplexed signal corresponding to a reception signal, the signal processor includes: an adaptive equalization circuit to compensate for the polarization demultiplexed signal by control of a filter coefficient; a first frequency offset estimation circuit to receive a first polarization demultiplexed signal diverged at a preceding stage and estimate a first frequency offset; a second frequency offset estimation circuit to receive a second polarization demultiplexed signal diverged at a succeeding stage and estimate a second frequency offset; and a decision circuit to decide whether the filter coefficient is correct based on a first difference between the first frequency offset and the second frequency offset and output, when deciding that the filter coefficient is incorrect, a first trigger for re-calculation of the filter coefficient.Type: ApplicationFiled: October 6, 2014Publication date: May 7, 2015Applicant: FUJITSU LIMITEDInventors: Kiichi Sugitani, Kazunari Shiota, Eri Katayama
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Patent number: 8934789Abstract: An optical digital coherent receiver includes: a polarization separation circuit configured to perform polarization separation on a received signal and output polarized signals; and a determination circuit configured to trigger a start of digital signal processing in a stage subsequent to the polarization separation circuit when it is determined that a distribution of a peak of an amplitude of one of the polarized signals has a characteristic corresponding to a modulation method used on a transmitting side.Type: GrantFiled: August 6, 2013Date of Patent: January 13, 2015Assignee: Fujitsu LimitedInventors: Kiichi Sugitani, Kazunari Shiota, Eri Katayama, Takahito Tanimura
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Publication number: 20140119731Abstract: An optical digital coherent receiver includes: a polarization separation circuit configured to perform polarization separation on a received signal and output polarized signals; and a determination circuit configured to trigger a start of digital signal processing in a stage subsequent to the polarization separation circuit when it is determined that a distribution of a peak of an amplitude of one of the polarized signals has a characteristic corresponding to a modulation method used on a transmitting side.Type: ApplicationFiled: August 6, 2013Publication date: May 1, 2014Applicant: FUJITSU LIMITEDInventors: Kiichi Sugitani, Kazunari Shiota, Eri Katayama, Takahito Tanimura
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Publication number: 20140064345Abstract: A signal processing apparatus includes a number P of adaptive equalization filters, P being 2 or more, configured to execute a first computing process for equalization on respective input signals, and to issue output signals; a number N of error calculation circuits, N being not more than P, configured to determine, per adaptive equalization filter, a second computing process to calculate an error in order to reduce a difference between a value of the output signal obtained with the first computing process and a predetermined objective value of the output signal; and an update circuit configured to determine a third computing process based on the second computing process determined per adaptive equalization filter by the error calculation circuit, and to update a computing process, which is executed in the adaptive equalization filter, to the third computing process.Type: ApplicationFiled: July 29, 2013Publication date: March 6, 2014Applicant: FUJITSU LIMITEDInventors: Kiichi Sugitani, Eri Katayama, Kazunari Shiota, Hisao Nakashima, Takeshi Hoshida
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Patent number: 8553825Abstract: A phase synchronization method uses a removal path for removing an error component contained in an input signal and a delay addition path for adding a delay corresponding to a processing time period taken to remove the error component in the removal path. The removal path includes an averaging section. The averaging section includes a shift register and an obtaining unit. The shift register stores as many data as the maximum number of data to be averaged and successively receives processing data from which the error component has been extracted in the removal path. The obtaining unit obtains, among the successive processing data input to the shift register, as many processing data as the number of data to be averaged from a position near the center toward both ends in the shift register.Type: GrantFiled: February 19, 2010Date of Patent: October 8, 2013Assignee: Fujitsu LimitedInventors: Kiichi Sugitani, Kazunari Shiota, Yuji Ishii, Hisao Nakashima
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Patent number: 8447190Abstract: A distortion compensating apparatus which compensates for distortion in a waveform of a received light signal through a digital signal processing includes a plurality of fixed amount compensators which compensate for the distortion in the waveform at respective given compensating amounts. The combination of operating states of the plurality of fixed amount compensators is changed by on/off switching of each of the plurality of fixed amount compensators, and the plurality of fixed amount compensators are cascaded.Type: GrantFiled: January 29, 2010Date of Patent: May 21, 2013Assignee: Fujitsu LimitedInventors: Takahito Tanimura, Takeshi Hoshida, Hisao Nakashima, Kazunari Shiota, Kiichi Sugitani
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Publication number: 20100239269Abstract: A phase synchronization method uses a removal path for removing an error component contained in an input signal and a delay addition path for adding a delay corresponding to a processing time period taken to remove the error component in the removal path. The removal path includes an averaging section. The averaging section includes a shift register and an obtaining unit. The shift register stores as many data as the maximum number of data to be averaged and successively receives processing data from which the error component has been extracted in the removal path. The obtaining unit obtains, among the successive processing data input to the shift register, as many processing data as the number of data to be averaged from a position near the center toward both ends in the shift register.Type: ApplicationFiled: February 19, 2010Publication date: September 23, 2010Applicant: FUJITSU LIMITEDInventors: Kiichi SUGITANI, Kazunari Shiota, Yuji Ishii, Hisao Nakashima
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Publication number: 20100196017Abstract: A distortion compensating apparatus which compensates for distortion in a waveform of a received light signal through a digital signal processing includes a plurality of fixed amount compensators which compensate for the distortion in the waveform at respective given compensating amounts. The combination of operating states of the plurality of fixed amount compensators is changed by on/off switching of each of the plurality of fixed amount compensators, and the plurality of fixed amount compensators are cascaded.Type: ApplicationFiled: January 29, 2010Publication date: August 5, 2010Applicant: FUJITSU LIMITEDInventors: Takahito TANIMURA, Takeshi Hoshida, Hisao Nakashima, Kazunari Shiota, Kiichi Sugitani
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Patent number: 7577098Abstract: A network monitoring device that monitors a network state, includes a receiving unit that receives a packet passing through the network; a processing unit that performs analysis of the network state with respect to the packet received; and a determining unit that determines whether a failure has occurred in the network, based on the result obtained by the processing unit.Type: GrantFiled: July 26, 2005Date of Patent: August 18, 2009Assignee: Fujitsu LimitedInventors: Nobuyuki Tamura, Tomonori Gotoh, Kazunari Shiota, Kiichi Sugitani, Ryota Komatsu
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Publication number: 20060209699Abstract: A network monitoring device that monitors a network state, includes a receiving unit that receives a packet passing through the network; a processing unit that performs analysis of the network state with respect to the packet received; and a determining unit that determines whether a failure has occurred in the network, based on the result obtained by the processing unit.Type: ApplicationFiled: July 26, 2005Publication date: September 21, 2006Inventors: Nobuyuki Tamura, Tomonori Gotoh, Kazunari Shiota, Kiichi Sugitani, Ryota Komatsu
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Patent number: 7106761Abstract: Data arriving from a plurality of channels asynchronously to each other are respectively stored in separate FIFOs (10). A controller (12) monitors the status of the FIFOs (10), retrieves the stored data in a predetermined order, and multiplexes the data, together with timing data indicating the presence or absence of the data, into a serial signal having a frame structure in which time slots are fixedly assigned to the respective channels. On the serial data, the same value appears successively as data, and when the data is valid, the corresponding timing data changes from a 0 to a 1. When the data is invalid, the value of the corresponding timing data does not change.Type: GrantFiled: February 13, 2002Date of Patent: September 12, 2006Assignee: Fujitsu LimitedInventors: Kazunari Shiota, Hidetoshi Kawamura, Seiji Miyahara, Isao Takata, Kanji Naito
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Patent number: 6785224Abstract: A ring configuring method configures a network in which a plurality of nodes are connected linearly, and performs topology construction for the ring by circulating topology data through the respective nodes and collecting connection information of the respective nodes. The method includes the steps of providing in the topology data a flag indicating whether the connection information is collected in each node; inverting the flag at a terminal station which is an end node of the open ring, and turning the topology data there; causing the topology data to passing through a node other than any terminal station as it is; and adding the connection information to the topology data in each node according to the flag, and performing topology construction.Type: GrantFiled: December 26, 2000Date of Patent: August 31, 2004Assignee: Fujitsu LimitedInventors: Kumiko Uematsu, Hiroshi Kanzawa, Takashi Honda, Junichi Moriyama, Kazunari Shiota, Hidetoshi Kawamura, Isao Takata, Yukie Yoshihara, Kanji Naito
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Publication number: 20020085593Abstract: Data arriving from a plurality of channels asynchronously to each other are respectively stored in separate FIFOs (10). A controller (12) monitors the status of the FIFOs (10), retrieves the stored data in a predetermined order, and multiplexes the data, together with timing data indicating the presence or absence of the data, into a serial signal having a frame structure in which time slots are fixedly assigned to the respective channels. On the serial data, the same value appears successively as data, and when the data is valid, the corresponding timing data changes from a 0 to a 1. When the data is invalid, the value of the corresponding timing data does not change.Type: ApplicationFiled: February 13, 2002Publication date: July 4, 2002Inventors: Kazunari Shiota, Hidetoshi Kawamura, Seiji Miyahara, Isao Takata, Kanji Naito
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Publication number: 20010019540Abstract: A ring configuring method configures a network in which a plurality of nodes are connected linearly, and performs topology construction for the ring by circulating topology data through the respective nodes and collecting connection information of the respective nodes. The method includes the steps of providing in the topology data a flag indicating whether the connection information is collected in each node; inverting the flag at a terminal station which is an end node of the open ring, and turning the topology data there; causing the topology data to passing through a node other than any terminal station as it is; and adding the connection information to the topology data in each node according to the flag, and performing topology construction.Type: ApplicationFiled: December 26, 2000Publication date: September 6, 2001Applicant: FUJITSU LIMITEDInventors: Kumiko Uematsu, Hiroshi Kanzawa, Takashi Honda, Junichi Moriyama, Kazunari Shiota, Hidetoshi Kawamura, Isao Takata, Yukie Yoshihara, Kanji Naito