Patents by Inventor Kazunari Shirai

Kazunari Shirai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7575012
    Abstract: A gas supply apparatus including: a tank unit that includes a tank storing a gas and a discharge mechanism discharging the stored gas to the outside of the tank at a reduced pressure of the stored gas; a temperature detector that detects a temperature of the tank; and a supply regulator that regulates supply of the gas from the tank according to the detected tank temperature.
    Type: Grant
    Filed: January 24, 2006
    Date of Patent: August 18, 2009
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Yoshiyuki Miki, Kazunari Shirai, Atsufumi Kimura, Naohiro Yoshida, Osamu Yumita
  • Publication number: 20060246177
    Abstract: A gas supply apparatus including: a tank unit that includes a tank storing a gas and a discharge mechanism discharging the stored gas to the outside of the tank at a reduced pressure of the stored gas; a temperature detector that detects a temperature of the tank; and a supply regulator that regulates supply of the gas from the tank according to the detected tank temperature.
    Type: Application
    Filed: January 24, 2006
    Publication date: November 2, 2006
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Yoshiyuki Miki, Kazunari Shirai, Atsufumi Kimura, Naohiro Yoshida, Osamu Yumita
  • Patent number: 6274993
    Abstract: A microcomputer produces to a drive circuit drive command signals for starting to drive and braking a motor so that the position of a throttle valve is controlled to a target position. A current supplied to the motor is limited not to exceed a first current limitation value at the time of motor drive start and braking. When the current limitation continues for a predetermined time period, the current is further limited not to exceed a second current limitation value. The microcomputer detects switching of motor current supply direction. When the current supply direction is switched, a reset command signal is produced to reset a timer operation for a current limitation continuation determination.
    Type: Grant
    Filed: March 10, 2000
    Date of Patent: August 14, 2001
    Assignee: Denso Corporation
    Inventors: Toru Itabashi, Kazunari Shirai
  • Patent number: 5669351
    Abstract: ECU performs a feedback control on a d.c. motor by a PID feedback control thereby to reduce errors between an actual throttle opening and a command throttle opening. PID control constants Kp, Ti and Td in the PID control are determined in accordance with operating conditions of a vehicle, such as engine idle speed control condition, vehicle traction control condition, vehicle cruise control condition and the like.
    Type: Grant
    Filed: February 26, 1996
    Date of Patent: September 23, 1997
    Assignee: Nippondenso Co., Ltd.
    Inventors: Kazunari Shirai, Hidemasa Miyano, Shigeru Kamio, Yoshimasa Nakaya
  • Patent number: 5669353
    Abstract: A throttle control system has two throttle opening sensors. When one sensor in a PID feedback control loop becomes abnormal, as sensed by monitoring the difference between outputs of the dual sensors, the use of sensor output for throttle feedback control is switched from the abnormal one to the other, normal one. Which one of the throttle opening sensors has become abnormal is determined by monitoring the intensity of electric current flowing to a DC motor which drives the throttle valve. Further, if an abnormality in the newly-used other sensor is determined, feedback control is continued based on an estimation of throttle opening calculated by using output of the sensor before its malfunction.
    Type: Grant
    Filed: March 6, 1996
    Date of Patent: September 23, 1997
    Assignee: Nippondenso Co., Ltd.
    Inventors: Kazunari Shirai, Hidemasa Miyano, Shigeru Kamio, Yoshimasa Nakaya
  • Patent number: 5640943
    Abstract: An air flow rate control apparatus for an internal combustion engine includes a stepping motor. The stepping motor has a plurality of coils and a rotor which is rotated by energizing the coils. A throttle valve connected to the rotor moves together with the rotor, and controls a rate of air flow drawn into the internal combustion engine. A control device is operative for feeding command currents of first and second command current values to first and second coils among the plurality of the coils respectively, and for controlling a degree of opening of the throttle valve. The first and second command current values correspond to a command degree of opening of the throttle valve at which the control device is intended to control the throttle valve. A direction of a resultant of vector forces generated by the first and second command currents simultaneously fed to the first and second coils corresponds to a held position of the rotor.
    Type: Grant
    Filed: May 10, 1995
    Date of Patent: June 24, 1997
    Assignee: Nippondenso Co., Ltd.
    Inventors: Hitoshi Tasaka, Kazunari Shirai, Yoshimasa Nakaya
  • Patent number: 5341301
    Abstract: This diversity type GPS system for a vehicle has first and second antennas mounted at first and second locations, respectively, inside a vehicle. First and second high frequency amplifiers and an antenna changer apply the signals received by the first and second antennas to first and second SS demodulators. The first and second SS demodulators simultaneously perform search operations for satellites, and demodulate rf signals (demodulated data) from the searched out satellites. An arithmetic and control unit computes a position of the vehicle from the demodulated data once three or more sets of demodulated data are available. The arithmetic and control unit also controls the antenna changer to switch the antenna from which a demodulator receives signals so as to improve the searching operations of the demodulators.
    Type: Grant
    Filed: December 23, 1991
    Date of Patent: August 23, 1994
    Assignee: Nippondenso Co., Ltd.
    Inventors: Kazunari Shirai, Yoshitaka Ozaki, Hiroyasu Fukaya
  • Patent number: 5214304
    Abstract: A semiconductor device comprises:a insulating film having a first part and a second part, the second part being thiner than the first part; and a polycrystalline silicon film having a first part arranged over the first part of the insulating film and a second part arranged over the second part of the insulating film, the second part of the polycrystalline silicon film having a lower concentration of impurities than that of the first part of the polycrystalline silicon film.
    Type: Grant
    Filed: March 12, 1992
    Date of Patent: May 25, 1993
    Assignee: Fujitsu Limited
    Inventors: Taiji Ema, Kazunari Shirai
  • Patent number: 4672740
    Abstract: A semiconductor device having contact windows between an aluminum or aluminum-alloy wiring layer and a diffused region in a semiconductor substrate, in which the contacts are formed by using a barrier film on a refractory metal silicide between the wiring layer and the diffused region. The barrier film comprising the refactory metal and silicon is beam annealed for a short period of time such as, 10 seconds or less, so that adverse effects of the barrier film can be prevented while an excellent electrical or ohmic contact between the wiring layer and the diffused layer can be obtained.
    Type: Grant
    Filed: August 28, 1984
    Date of Patent: June 16, 1987
    Assignee: Fujitsu Limited
    Inventors: Kazunari Shirai, Hajime Kamioka, Shigeyoshi Koike
  • Patent number: 4500899
    Abstract: The present invention is an improvement of a semiconductor memory device, preferably a PROM or a mask ROM, wherein: MOS transistors are formed in a semiconductor substrate, are arranged in rows, and are isolated from each other by a plurality of field insulation films arranged in an island pattern; the MOS transistors aligned in one of the rows have one common gate which extends over one row of field insulation films; the MOS transistors aligned in one of the rows have a common first region for forming a drain or a source parallel to the common gates; and a second region for forming another drain or source is surrounded by a pair of common gates and a pair of field insulation films so that a plurality of second regions are isolated from each other.
    Type: Grant
    Filed: December 23, 1981
    Date of Patent: February 19, 1985
    Assignee: Fujitsu Limited
    Inventors: Kazunari Shirai, Izumi Tanaka
  • Patent number: 4405995
    Abstract: An improved semiconductor memory device is provided, which has: (i) a first gate electrode in an electrically floating state, at least a part of which confronts a channel region of a semiconductor device and which is separated by an insulating layer from the channel region; (ii) a second gate electrode (i.e., a control electrode), at least a part of which confronts the first gate electrode and is separated by an insulating layer from the first gate electrode; and (iii) a third gate electrode (i.e., an erasing electrode), at least a part of which confronts the first gate electrode and is separated by an insulating layer from the first gate electrode. The insulating layer, separating at least a part of the erasing electrode from the first gate electrode, has a thickness (usually 50 to 300 A) sufficient to allow the passage of charges from the first gate electrode to the erasing electrode through a tunneling effect, thereby discharging the first gate electrode.
    Type: Grant
    Filed: August 24, 1981
    Date of Patent: September 20, 1983
    Assignee: Fujitsu Limited
    Inventors: Kazunari Shirai, Izumi Tanaka
  • Patent number: 4399451
    Abstract: A plural layered wiring which comprises a plurality of polycrystal semiconductor layers can be improved in its magnitude of circuit integration, when one or more upper polycrystal semiconductor layers which is or are doped to a moderate impurity concentration is or are utilized as resistor elements, the lowest polycrystal semiconductor layer which is highly doped is utilized for electrodes and/or wirings for active elements, and both polycrystal layers are connected with each other by regions which are highly doped by upward diffusion of impurities contained in highly doped regions of a substrate, because this configuration entirely avoids the restriction that is imposed for the location of resistor elements arranged in the upper layers. This arrangement is realized by a specific sequential combination of steps which includes a step of upward diffusion of impurities from the highly doped regions of the substrate. An additional advantage of this method is the exclusion of a so-called non-butting process.
    Type: Grant
    Filed: December 30, 1980
    Date of Patent: August 16, 1983
    Assignee: Fujitsu Limited
    Inventor: Kazunari Shirai
  • Patent number: 4326213
    Abstract: A polycrystalline silicon is used for a resistor element of a semiconductor device instead of a conventional, diffused resistor or a channel resistor, in which the channel resistance of an MOS transistor is utilized as the resistor. The length of a polycrystalline silicon layer for the resistor element is predetermined by the other polycrystalline silicon layer, formed above the resistor element. The structure of the semiconductor device according to the present invention is suited for a high density integrated circuit.
    Type: Grant
    Filed: November 29, 1978
    Date of Patent: April 20, 1982
    Assignee: Fujitsu Limited
    Inventors: Kazunari Shirai, Izumi Tanaka
  • Patent number: 4271582
    Abstract: In a method of smoothing the edges of a window through a PSG film of a semiconductor device, a masking film is provided under the PSG film, so as to prevent impurities of the PSG film from penetrating into semiconductor substrate during the heating of the PSG film for the smoothing of the edges. A masking film, for example, an Si.sub.3 N.sub.4 film, does not, however, inhibit the penetration of hydrogen gas, which can improve the properties of an MIS semiconductor device.
    Type: Grant
    Filed: August 29, 1979
    Date of Patent: June 9, 1981
    Assignee: Fujitsu Limited
    Inventors: Kazunari Shirai, Izumi Tanaka, Shinpei Tanaka, Keiji Nishimoto
  • Patent number: 3937821
    Abstract: A process for preparing a pyrogen-free plasma substitute consisting of treating hydroxyethyl starch having a DS of 0.5 - 0.6 (preferably 0.55) and an intrinsic viscosity of 0.28 - 0.30 with an acid to lower the molecular weight; adjusting it to the desired hydroxyethyl starch having a DS of 0.55 and an intrinsic viscosity of 0.08- 0.14; adding a depyrogen reagent, such as Raney-nickel to it, if necessary, obtaining an isotonic aqueous solution containing 6% of hydroxyethyl starch and other various salts, preferably, adding sodium chloride (0.5%), potassium chloride (0.03%), calcium chloride dihydrate (0.02%), sodium lactate (0.224%), and glucose (1%)(W/V%) to 6% hydroxyethyl starch solution; and then adjusting the pH of the obtained iostonic aqueous solution to 6.2 .+-. 0.5.
    Type: Grant
    Filed: November 19, 1973
    Date of Patent: February 10, 1976
    Assignee: Kyorin Seiyaku Kabushiki Kaisha
    Inventors: Tsutomu Irikura, Kazunari Shirai, Mamoru Tada, Terumi Tamada, Jun Imai