Patents by Inventor Kazunari Suga

Kazunari Suga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11693049
    Abstract: A sensor test apparatus capable of efficiently testing a sensor is provided. A sensor test apparatus 30 which tests the pressure sensor 90 includes an application unit 40 including an application device 42 including a socket 445 to which the sensor 90 is electronically connected, a pressure chamber 43 which applies pressure to the sensor 90, and a heat sink 443,462 which applies a thermal stress to the sensor 90, the test unit 35 which tests the sensor 90 via the socket 445, and the conveying robot 33 which conveys the sensor 90 into and out of the application unit 40.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: July 4, 2023
    Assignee: ADVANTEST Corporation
    Inventors: Kazunari Suga, Daisuke Takano, Satoshi Hanamura, Michiro Chiba, Hisao Nishizaki, Atsushi Hayakawa
  • Patent number: 11614350
    Abstract: A sensor test apparatus having excellent versatility is provided. The sensor test apparatus includes a first application unit 40 including a first application device including a socket to which the sensor is electrically connected, and a pressure chamber 43 which applies pressure to the sensor, a test unit which tests the sensor 90 via the socket, a conveying robot which conveys the sensor into and out of the first application unit 40, and an apparatus main body which houses the first application unit 40, the test unit 35 and the conveying robot, and the apparatus main body has an opening which allows the first application unit 40 to be inserted into the apparatus main body and removed from the apparatus main body to an outside.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: March 28, 2023
    Assignee: ADVANTEST Corporation
    Inventors: Kazunari Suga, Daisuke Takano, Satoshi Hanamura, Michiro Chiba, Hisao Nishizaki, Atsushi Hayakawa
  • Patent number: 11460520
    Abstract: A sensor test system having excellent throughput is provided. The sensor test system 1 includes a test apparatus group 20 including a plurality of sensor test apparatuses 30A to 30D coupled to each other so that the sensor 90 can be transferred, and each of the sensor test apparatuses 30A to 30D includes an application unit 40 including an application device 42 including a socket 445 to which the sensor 90 is electrically connected, and a pressure chamber 43 which applies a pressure to the sensor 90, a test unit 35 which tests the sensor 90 via the socket 445, and a conveying robot 33 which conveys the sensor 90 into and out of the application unit 40.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: October 4, 2022
    Assignee: ADV ANTEST Corporation
    Inventors: Kazunari Suga, Daisuke Takano, Satoshi Hanamura, Michiro Chiba, Hisao Nishizaki, Atsushi Hayakawa
  • Publication number: 20200191886
    Abstract: A sensor test system having excellent throughput is provided. The sensor test system 1 includes a test apparatus group 20 including a plurality of sensor test apparatuses 30A to 30D coupled to each other so that the sensor 90 can be transferred, and each of the sensor test apparatuses 30A to 30D includes an application unit 40 including an application device 42 including a socket 445 to which the sensor 90 is electrically connected, and a pressure chamber 43 which applies a pressure to the sensor 90, a test unit 35 which tests the sensor 90 via the socket 445, and a conveying robot 33 which conveys the sensor 90 into and out of the application unit 40.
    Type: Application
    Filed: September 19, 2019
    Publication date: June 18, 2020
    Applicant: ADVANTEST Corporation
    Inventors: Kazunari Suga, Daisuke Takano, Satoshi Hanamura, Michiro Chiba, Hisao Nishizaki, Atsushi Hayakawa
  • Publication number: 20200191864
    Abstract: A sensor test apparatus capable of efficiently testing a sensor is provided. A sensor test apparatus 30 which tests the pressure sensor 90 includes an application unit 40 including an application device 42 including a socket 445 to which the sensor 90 is electronically connected, a pressure chamber 43 which applies pressure to the sensor 90, and a heat sink 443,462 which applies a thermal stress to the sensor 90, the test unit 35 which tests the sensor 90 via the socket 445, and the conveying robot 33 which conveys the sensor 90 into and out of the application unit 40.
    Type: Application
    Filed: September 19, 2019
    Publication date: June 18, 2020
    Applicant: ADVANTEST Corporation
    Inventors: Kazunari Suga, Daisuke Takano, Satoshi Hanamura, Michiro Chiba, Hisao Nishizaki, Atsushi Hayakawa
  • Publication number: 20200191622
    Abstract: A sensor test apparatus having excellent versatility is provided. The sensor test apparatus 30 includes a first application unit 40 including a first application device 42 including a socket 445 to which the sensor 90 is electrically connected, and a pressure chamber 43 which applies pressure to the sensor 90, a test unit 35 which tests the sensor 90 via the socket 445, a conveying robot 33 which conveys the sensor 90 into and out of the first application unit 40, and an apparatus main body 301 which houses the first application unit 40, the test unit 35 and the conveying robot 33, and the apparatus main body 301 has an opening 306d which allows the first application unit 40 to be inserted into the apparatus main body 301 and removed from the apparatus main body 301 to an outside.
    Type: Application
    Filed: September 19, 2019
    Publication date: June 18, 2020
    Applicant: ADVANTEST Corporation
    Inventors: Kazunari Suga, Daisuke Takano, Satoshi Hanamura, Michiro Chiba, Hisao Nishizaki, Atsushi Hayakawa
  • Publication number: 20090230985
    Abstract: A burn-in system enabling the temperatures of a large number of electronic devices differing in amount of self generated heat to be simultaneously reliably adjusted to a predetermined temperature, that is, a burn-in system bringing heater blocks having heaters, cooling blocks formed with channels able to carry a coolant, and sensor blocks having temperature sensors into contact with a plurality of DUTs mounted on a burn-in board and simultaneously performing a burn-in test on the plurality of DUTs, wherein each cooling block is formed with a first accommodating space and second accommodating space, each heater block is accommodated in a first accommodating space in a state maintaining clearance from the inside wall surfaces, and each sensor block is accommodated in a second accommodating space in a state maintaining clearance from the inside wall surfaces.
    Type: Application
    Filed: May 18, 2009
    Publication date: September 17, 2009
    Applicant: ADVANTEST Corporation
    Inventors: Kazunari Suga, Toru Honobe, Seigo Matsunaga, Kazumi Kita
  • Patent number: 7554350
    Abstract: A burn-in system enabling the temperatures of a large number of electronic devices differing in amount of self generated heat to be simultaneously reliably adjusted to a predetermined temperature, that is, a burn-in system bringing heater blocks having heaters, cooling blocks formed with channels able to carry a coolant, and sensor blocks having temperature sensors into contact with a plurality of DUTs mounted on a burn-in board and simultaneously performing a burn-in test on the plurality of DUTs, wherein each cooling block is formed with a first accommodating space and second accommodating space, each heater block is accommodated in a first accommodating space in a state maintaining clearance from the inside wall surfaces, and each sensor block is accommodated in a second accommodating space in a state maintaining clearance from the inside wall surfaces.
    Type: Grant
    Filed: May 7, 2008
    Date of Patent: June 30, 2009
    Assignee: Advantest Corporation
    Inventors: Kazunari Suga, Toru Honobe, Seigo Matsunaga, Kazumi Kita
  • Publication number: 20080238465
    Abstract: A burn-in system enabling the temperatures of a large number of electronic devices differing in amount of self generated heat to be simultaneously reliably adjusted to a predetermined temperature, that is, a burn-in system bringing heater blocks having heaters, cooling blocks formed with channels able to carry a coolant, and sensor blocks having temperature sensors into contact with a plurality of DUTs mounted on a burn-in board and simultaneously performing a burn-in test on the plurality of DUTs, wherein each cooling block is formed with a first accommodating space and second accommodating space, each heater block is accommodated in a first accommodating space in a state maintaining clearance from the inside wall surfaces, and each sensor block is accommodated in a second accommodating space in a state maintaining clearance from the inside wall surfaces.
    Type: Application
    Filed: May 7, 2008
    Publication date: October 2, 2008
    Inventors: Kazunari SUGA, Toru Honobe, Seigo Matsunaga, Kazumi Kita
  • Patent number: 7397258
    Abstract: A burn-in system enabling the temperatures of a large number of electronic devices differing in amount of self generated heat to be simultaneously reliably adjusted to a predetermined temperature, that is, a burn-in system bringing heater blocks having heaters, cooling blocks formed with channels able to carry a coolant, and sensor blocks having temperature sensors into contact with a plurality of DUTs mounted on a burn-in board and simultaneously performing a burn-in test on the plurality of DUTs, wherein each cooling block is formed with a first accommodating space and second accommodating space, each heater block is accommodated in a first accommodating space in a state maintaining clearance from the inside wall surfaces, and each sensor block is accommodated in a second accommodating space in a state maintaining clearance from the inside wall surfaces.
    Type: Grant
    Filed: September 15, 2005
    Date of Patent: July 8, 2008
    Assignee: Advantest Corporation
    Inventors: Kazunari Suga, Toru Honobe, Seigo Matsunaga, Kazumi Kita
  • Publication number: 20070057686
    Abstract: A burn-in system enabling the temperatures of a large number of electronic devices differing in amount of self generated heat to be simultaneously reliably adjusted to a predetermined temperature, that is, a burn-in system bringing heater blocks having heaters, cooling blocks formed with channels able to carry a coolant, and sensor blocks having temperature sensors into contact with a plurality of DUTs mounted on a burn-in board and simultaneously performing a burn-in test on the plurality of DUTs, wherein each cooling block is formed with a first accommodating space and second accommodating space, each heater block is accommodated in a first accommodating space in a state maintaining clearance from the inside wall surfaces, and each sensor block is accommodated in a second accommodating space in a state maintaining clearance from the inside wall surfaces.
    Type: Application
    Filed: September 15, 2005
    Publication date: March 15, 2007
    Inventors: Kazunari Suga, Toru Honobe, Seigo Matsunaga, Kazumi Kita
  • Patent number: 6292005
    Abstract: A probe card 2 for an IC testing apparatus electrically connected to a test head board 11 of the IC testing apparatus and having a plurality of needle contacts 211 provided on a main surface for electrical contact with a device under test, wherein a plurality of zero insertion force connectors electrically connected to the needle contacts are provided at substantially radial positions from the position where the needle contacts are provided.
    Type: Grant
    Filed: July 7, 1999
    Date of Patent: September 18, 2001
    Assignee: Advantest Corporatin
    Inventor: Kazunari Suga
  • Patent number: 6184697
    Abstract: A main frame of an IC testing apparatus is formed in the shape of a horizontally elongated box with its height close to the height of wafer probers. Two wafer probers are arranged side by side transversely of the main frame on the front said thereof. One rotary drive is equipped with two output shafts which are connected via respective clutches with the rotary drive, and the testing heads are connected to the associated output shafts. The rotary drive is disposed on the top of the main frame with an extension of the upper portion of the rotary drive, and is adapted to rotatively drive the testing heads connected to the output shifts between a fist position opposing the contact section of the associated wafer prober and a second position over the top of the main frame. This construction reduces the installation areas for each of the wafer probers as well as narrowing the space between the wafer probers and the main frame.
    Type: Grant
    Filed: February 24, 1997
    Date of Patent: February 6, 2001
    Assignee: Advantest Corporation
    Inventor: Kazunari Suga
  • Patent number: 6075372
    Abstract: A main frame of an IC testing apparatus is formed in the shape of a horizontally elongated box with its height close to the height of wafer probers. Two wafer probers are arranged side by side transversely of the main frame on the front said thereof. One rotary drive is equipped with two output shafts which are connected via respective clutches with the rotary drive, and the testing heads are connected to the associated output shafts. The rotary drive is disposed on the top of the main frame with an extension of the upper portion of the rotary drive, and is adapted to rotatively drive the testing heads connected to the output shifts between a fist position opposing the contact section of the associated wafer prober and a second position over the top of the main frame. This construction reduces the installation areas for each of the wafer probers as well as narrowing the space between the wafer probers and the main frame.
    Type: Grant
    Filed: February 24, 1997
    Date of Patent: June 13, 2000
    Assignee: Advantest Corporation
    Inventor: Kazunari Suga
  • Patent number: 6052284
    Abstract: A cooler-equipped printed circuit board, in which electronic devices arranged in a matrix form on the printed circuit board are covered with a sealed case held in liquidtight contact with the board and having a coolant channel from an inlet port and an outlet port made in the case. Barriers are provided in the coolant channel to change the direction of flow of the coolant to stir it and make its temperature uniform throughout it.
    Type: Grant
    Filed: July 29, 1997
    Date of Patent: April 18, 2000
    Assignee: Advantest Corporation
    Inventors: Kazunari Suga, Akihiro Fujimoto
  • Patent number: 5818219
    Abstract: A semiconductor test system having a test head connection apparatus for connecting and disconnecting a test head of the test system with a wafer prober or a test handler includes a housing formed outside of the semiconductor test system wherein the housing is integral with a body of the test system, a pair of arms provide on the housing for holding the test head wherein the test head rotates about 180 degrees in the arms so that a performance board on the test head faces with a corresponding member on the wafer prober or the test handler, at least one rail built on a floor in a direction which accurately positioning the test head right over the wafer prober or the test handler, a guide mechanism provided on the housing to guide an up-down movement of the arms, a plurality of free casters provided at the bottom of the housing to transfer the test system and the test head toward the wafer prober or the test handler along the rail, and a balancing mechanism for offsetting the weight of the test head so that the
    Type: Grant
    Filed: November 22, 1995
    Date of Patent: October 6, 1998
    Assignee: Advantest Corp.
    Inventors: Hiroyuki Hama, Kazunari Suga
  • Patent number: 5754057
    Abstract: A contact mechanism is for a test head of a semiconductor test system for connecting the test head to a wafer prober or a test handler having a semiconductor device to be tested. The contact mechanism includes, a performance board mounted between the test head the wafer prober wherein the performance board has a guide hole, an insert ring mounted on a frame of the wafer prober, a probe card mounted on a central portion of the insert ring for contacting the semiconductor device to be tested, a contactor having a plurality of contact pins to achieve electric contact between the performance board and the probe card when pressed in downward by the performance board, a performance board shaft extending from a bottom of the test head and penetrating the guide hole of the performance board, a shaft clamp provided on the insert ring having a shaft guide hole to receive the performance board shaft therethrough wherein a bottom of the shaft guide hole is lower than a surface of the insert ring.
    Type: Grant
    Filed: January 24, 1996
    Date of Patent: May 19, 1998
    Assignee: Advantest Corp.
    Inventors: Hiroyuki Hama, Kazunari Suga
  • Patent number: 5747994
    Abstract: A board exchange mechanism for a self-diagnosis process excludes the need of disconnecting a test head from a wafer prober for installing a self-diagnosis board.
    Type: Grant
    Filed: April 26, 1996
    Date of Patent: May 5, 1998
    Assignee: Advantest Corp.
    Inventor: Kazunari Suga