Abstract: A level shift output circuit includes a level shifter interconnecting first and second power supplies that supply first and second voltages, the second being lower than the first voltage. The circuit outputs complimentary first and second output signals responsive to complimentary first and second input signals. High breakdown voltage inverters interconnect the first and second power supplies, and are configured to output a third output signal responsive to a first control signal and the first output signal from the level shifter and output a fourth output signal which is complimentary with the third output signal, responsive to a second control signal complimentary with the first control signal, and the second output signal. P-type transistors interconnect the first power supply and a power supply output node, and respectively supply the first voltage to the power supply output node in response to the fourth output signals from the high breakdown voltage inverters.

Abstract: An output buffer circuit constituted by a totem-pole circuit where two NchMOS transistors are cascade-connected, and the connection point of the two MOS transistors are connected to a data electrode of a display cell, improves the power recovery rate of a driver device of a PDP. A level shift circuit includes a CMOS circuit and drives the output buffer circuit. An electric charge recovery circuit connected to a power supply of the output buffer circuit recovers and reuses electric charges remaining on the data electrode after the discharge of the display cells. A power supply control circuit controls so that the power supply voltage of the level shift circuit is higher than the sum of the power supply voltage of the output buffer circuit and the threshold voltage of the MOS transistors for a period of time during a recovery/reuse cycle of the electric charge recovery circuit.

Abstract: A PDP data driver is provided in which input and output terminals are divided into a plurality of groups and a given group can be selected so as to output a high level. The PDP data driver is formed by a plurality of data driver ICs that are arranged. In an output control circuit of each data driver IC, input and output terminals are arranged in an order of a plurality of primary colors forming a screen and are divided into a plurality of groups. The output control circuit includes a first gate array and a second gate array in such a manner that gates of each array corresponds to the input and output terminals, respectively. For each of the groups, the first gate array is controlled to output input data without change or output a high level in accordance with a first control input and the second gate array is controlled to transfer all outputs of the first gate array without change or output a low level in accordance with a second control output.

Abstract: To improve the power recovery rate of a driver device of a PDP. An output buffer circuit 10 is constituted by a totem-pole circuit where two NchMOS transistors Q1 and Q2 are cascade-connected, and the connection point (VOUT) of the two MOS transistors are connected to a data electrode C0 of a display cell. A level shift circuit 11 is constituted by a CMOS circuit and drives the output buffer circuit 10. An electric charge recovery circuit 13 is connected to a power supply VDD2 of the output buffer circuit 10, and it recovers and reuses electric charges remaining on the data electrode C0 after the discharge of the display cells. A power supply control circuit 12 controls so that the power supply voltage of the level shift circuit 11 is higher than the sum of the power supply voltage of the output buffer circuit 10 and the threshold voltage of the MOS transistors for a period of time during a recovery/reuse cycle of the electric charge recovery circuit 13.

Abstract: A PDP data driver is provided in which input and output terminals are divided into a plurality of groups and a given group can be selected so as to output a high level. The PDP data driver is formed by a plurality of data driver ICs that are arranged. In an output control circuit of each data driver IC, input and output terminals are arranged in an order of a plurality of primary colors forming a screen and are divided into a plurality of groups. The output control circuit includes a first gate array and a second gate array in such a manner that gates of each array corresponds to the input and output terminals, respectively. For each of the groups, the first gate array is controlled to output input data without change or output a high level in accordance with a first control input and the second gate array is controlled to transfer all outputs of the first gate array without change or output a low level in accordance with a second control output.

Abstract: A semiconductor device in which the potential of a conductive support substrate can be kept to be a predetermined potential, while an SOI substrate is used as a chip substrate, without adding a new step and providing a rear electrode, is provided. In a chip, on the main surface of a first Si substrate of a P-type, a SiO2 film and a second Si substrate of a P-type are laminated in this order. The chip has, in the second Si substrate, isolation trenches, an outermost isolation trench, a plurality of element forming regions isolated by these trenches, second element forming regions, a peripheral region, and a peripheral region connection wiring which connects a contact region of the peripheral region with a contact region connected with a predetermined potential, for example, a ground potential in the second element forming region surrounded by, for example, the isolation trench.

Abstract: A probe card includes low-voltage and high-voltage source pins and a plurality of signal pins. An EMI filter block is electrically connected between each source pin and a corresponding card terminal. Each EMI filter block includes a plurality of EMI filter elements connected in parallel. The low-voltage EMI filter element includes a three-terminal capacitor and a ferrite bead separately disposed, whereas the high-voltage EMI filter element includes a three-terminal capacitor having a built-in ferrite bead.

Abstract: A semiconductor device in which the potential of a conductive support substrate can be kept to be a predetermined potential, while an SOI substrate is used as a chip substrate, without adding a new step and providing a rear electrode, is provided. In a chip, on the main surface of a first Si substrate of a P-type, a SiO2 film and a second Si substrate of a P-type are laminated in this order. The chip has, in the second Si substrate, isolation trenches, an outermost isolation trench, a plurality of element forming regions isolated by these trenches, second element forming regions, a peripheral region, and a peripheral region connection wiring which connects a contact region of the peripheral region with a contact region connected with a predetermined potential, for example, a ground potential in the second element forming region surrounded by, for example, the isolation trench.