Patents by Inventor Kazunari Tamura
Kazunari Tamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11901234Abstract: There is provided a method of processing a wafer having devices formed in respective areas on a face side thereof that are demarcated by a plurality of crossing projected dicing lines on the face side. The method of processing a wafer includes a wafer unit forming step of forming a wafer unit having a wafer, a tape, and an annular frame, a dividing step of dividing the wafer along the projected dicing lines into a plurality of device chips, a pick-up step of picking up one at a time of the device chips from the wafer unit, and a measuring step of measuring the device chip picked up in the pick-up step. The method also includes a distinguishing step, before the pick-up step, of inspecting properties of the devices to distinguish acceptable devices and defective devices among the devices and storing distinguished results.Type: GrantFiled: March 15, 2023Date of Patent: February 13, 2024Assignee: DISCO CORPORATIONInventors: Takashi Mori, Makoto Kobayashi, Kazunari Tamura, Okito Umehara
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Publication number: 20230223303Abstract: There is provided a method of processing a wafer having devices formed in respective areas on a face side thereof that are demarcated by a plurality of crossing projected dicing lines on the face side. The method of processing a wafer includes a wafer unit forming step of forming a wafer unit having a wafer, a tape, and an annular frame, a dividing step of dividing the wafer along the projected dicing lines into a plurality of device chips, a pick-up step of picking up one at a time of the device chips from the wafer unit, and a measuring step of measuring the device chip picked up in the pick-up step. The method also includes a distinguishing step, before the pick-up step, of inspecting properties of the devices to distinguish acceptable devices and defective devices among the devices and storing distinguished results.Type: ApplicationFiled: March 15, 2023Publication date: July 13, 2023Inventors: Takashi MORI, Makoto KOBAYASHI, Kazunari TAMURA, Okito UMEHARA
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Patent number: 11637039Abstract: There is provided a method of processing a wafer having devices formed in respective areas on a face side thereof that are demarcated by a plurality of crossing projected dicing lines on the face side. The method of processing a wafer includes a wafer unit forming step of forming a wafer unit having a wafer, a tape, and an annular frame, a dividing step of dividing the wafer along the projected dicing lines into a plurality of device chips, a pick-up step of picking up one at a time of the device chips from the wafer unit, and a measuring step of measuring the device chip picked up in the pick-up step. The method also includes a distinguishing step, before the pick-up step, of inspecting properties of the devices to distinguish acceptable devices and defective devices among the devices and storing distinguished results.Type: GrantFiled: September 17, 2020Date of Patent: April 25, 2023Assignee: DISCO CORPORATIONInventors: Takashi Mori, Makoto Kobayashi, Kazunari Tamura, Okito Umehara
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Patent number: 11474143Abstract: A testing apparatus for measuring a strength of a chip includes: a cassette mounting base on which to mount a cassette capable of accommodating wafer units; a frame fixing mechanism that fixes an annular frame of the wafer unit; a conveying mechanism that conveys the wafer unit between the cassette and the frame fixing mechanism; a pushing-up mechanism that pushes up a predetermined chip included in the wafer supported by the annular frame fixed by the frame fixing mechanism; a pick-up mechanism having a collet picking up the chip pushed up by the pushing-up mechanism; a strength measuring mechanism having a support unit supporting the chip picked up by the collet; and a collet moving mechanism that moves the collect from a position facing the pushing-up mechanism to a position facing the support unit.Type: GrantFiled: December 9, 2019Date of Patent: October 18, 2022Assignee: DISCO CORPORATIONInventors: Makoto Kobayashi, Okito Umehara, Yoshinobu Saito, Yusaku Ito, Hirohide Yano, Kazunari Tamura
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Publication number: 20210090954Abstract: There is provided a method of processing a wafer having devices formed in respective areas on a face side thereof that are demarcated by a plurality of crossing projected dicing lines on the face side. The method of processing a wafer includes a wafer unit forming step of forming a wafer unit having a wafer, a tape, and an annular frame, a dividing step of dividing the wafer along the projected dicing lines into a plurality of device chips, a pick-up step of picking up one at a time of the device chips from the wafer unit, and a measuring step of measuring the device chip picked up in the pick-up step. The method also includes a distinguishing step, before the pick-up step, of inspecting properties of the devices to distinguish acceptable devices and defective devices among the devices and storing distinguished results.Type: ApplicationFiled: September 17, 2020Publication date: March 25, 2021Inventors: Takashi MORI, Makoto KOBAYASHI, Kazunari TAMURA, Okito UMEHARA
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Publication number: 20200182923Abstract: A testing apparatus for measuring a strength of a chip includes: a cassette mounting base on which to mount a cassette capable of accommodating wafer units; a frame fixing mechanism that fixes an annular frame of the wafer unit; a conveying mechanism that conveys the wafer unit between the cassette and the frame fixing mechanism; a pushing-up mechanism that pushes up a predetermined chip included in the wafer supported by the annular frame fixed by the frame fixing mechanism; a pick-up mechanism having a collet picking up the chip pushed up by the pushing-up mechanism; a strength measuring mechanism having a support unit supporting the chip picked up by the collet; and a collet moving mechanism that moves the collect from a position facing the pushing-up mechanism to a position facing the support unit.Type: ApplicationFiled: December 9, 2019Publication date: June 11, 2020Inventors: Makoto KOBAYASHI, Okito UMEHARA, Yoshinobu SAITO, Yusaku ITO, Hirohide YANO, Kazunari TAMURA
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Publication number: 20090194023Abstract: A plasma processing apparatus is provided which can suppress variation in the electrode impedance varying due to a product or the like attached in a processing chamber, and which prevents variation in electric power consumed for plasma. According to the present invention, a plasma processing apparatus comprises a radiofrequency power supply 5 outputting radiofrequency power with reference to GND; a switching device 24 connected to the radiofrequency power supply; a lower electrode 2 connected to the switching device 24; an impedance control device 22 connected between the lower electrode 2 and GND; an impedance measuring device 23 connected between the switching device 24 and GND; and a controller 26 controlling the impedance control device 22 according to the value of impedance (the electrode impedance) measured by the impedance measuring device 23.Type: ApplicationFiled: January 22, 2009Publication date: August 6, 2009Applicant: NEC Electronics CorporationInventor: Kazunari Tamura
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Patent number: 7235686Abstract: A process for preparing a phosphoric ester, comprising: Step (1) of reacting naphthol with phosphorus oxychloride in a molar ratio of 1:1.3 or more in the presence of a metallic halide and removing unreacted phosphorus oxychloride and Step (2) of reacting the reaction product of Step (1) with phenol in a molar ratio (molar ratio of chlorine contained in the reaction product to phenol) of 1:1–1.5 and removing hydrogen chloride produced as a by-product to thereby obtain a phosphoric ester represented by the general formula (I): wherein n is 1 or 2.Type: GrantFiled: April 25, 2002Date of Patent: June 26, 2007Assignee: Daihachi Chemical Industry Co., Ltd.Inventor: Kazunari Tamura
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Publication number: 20040254390Abstract: A process for preparing a phosphoric ester, comprising: Step (1) of reacting naphthol with phosphorus oxychloride in a molar ratio of 1:1.3 or more in the presence of a metallic halide and removing unreacted phosphorus oxychloride and Step (2) of reacting the reaction product of Step (1) with phenol in a molar ratio (molar ratio of chlorine contained in the reaction product to phenol) of 1:1-1.Type: ApplicationFiled: August 10, 2004Publication date: December 16, 2004Inventor: Kazunari Tamura