Abstract: A semiconductor device includes: a semiconductor substrate, an element isolation insulating layer disposed on the semiconductor substrate, and a plurality of conductive layers opposed to the semiconductor substrate and the element isolation insulating layer. The semiconductor substrate includes a first active region and a second active region arranged in a first direction along a main surface. The first element isolation insulating layer is disposed between the first active region and the second active region. The plurality of conductive layers include a first electrode and a second electrode opposed to the element isolation insulating layer in a second direction intersecting with the main surface of the semiconductor substrate, and arranged in the first direction, the first electrode being disposed on the first active region side and the second electrode disposed on the second active region side.

Abstract: A semiconductor memory device includes: a first transistor including a substrate including first and second regions of first conductive type, a first insulating film provided on the first and second regions, a first wiring of first conductive type provided on the first region, being electrically connected to the first region, and including a higher impurity concentration of first conductive type than an impurity concentration of the first region, and a second wiring of first conductive type provided on the second region, being electrically connected to the second region, and including a higher impurity concentration of first conductive type than an impurity concentration of the second region; a conductive layer provided parallel to a substrate plane above the first transistor; a pillar penetrating the conductive layer, the pillar including a semiconductor film; and a charge storage film provided between the semiconductor film and the conductive layer.

Abstract: A semiconductor memory device according to an embodiment includes: a first transistor, the first transistor including a substrate including a first region of first conductive type and a second region of first conductive type, a first insulating film provided on the first region and the second region, a first wiring of first conductive type provided on the first region, the first wiring being electrically connected to the first region, and the first wiring including a higher impurity concentration of first conductive type than an impurity concentration of the first region, and a second wiring of first conductive type provided on the second region, the second wiring being electrically connected to the second region, and the second wiring including a higher impurity concentration of first conductive type than an impurity concentration of the second region; a conductive layer provided parallel to a substrate plane above the first transistor; a pillar penetrating the conductive layer, the pillar including a semico

Abstract: A nonvolatile semiconductor memory device includes a semiconductor substrate, a memory element including a first gate electrode having a first thickness disposed on a first insulation film on the semiconductor substrate, and a first peripheral element other than a memory element including a second gate electrode having a second thickness disposed on a second insulation film on the semiconductor substrate. The first gate electrode and second gate electrode comprise a plurality of film layers, and the configuration of the film layers are different as between the first gate electrode of the memory element and the second gate electrode of the peripheral element, and the first thickness is different from the second thickness.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor substrate a memory element that includes a first gate electrode having a first height on the semiconductor substrate through a first insulation film, and a peripheral element other than the memory element that includes a second gate electrode having a second height on the semiconductor substrate through a second insulation film, in which stacked structures of gate materials are different between the first gate electrode of the memory element and the second gate electrode of the peripheral element, and the first height of the first gate electrode is different from the second height of the second gate electrode.