Patents by Inventor Kazunobu Miki
Kazunobu Miki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8178981Abstract: The present invention aims at offering the semiconductor device which can improve the strength to the stress generated with a bonding pad. In the semiconductor device concerning the present invention, a plurality of bonding pads are formed on a semiconductor chip. In each bonding pad, a plurality of second line-like metals are formed under the first metal formed using the wiring layer of the top layer. And a bonding pad is put in order and located along the long-side direction of a second metal to achieve the above objects. That is, a bonding pad is put in order and located so that the long-side direction of a second metal and the arrangement direction of a bonding pad may become in the same direction.Type: GrantFiled: March 2, 2010Date of Patent: May 15, 2012Assignee: Renesas Electronics CorporationInventors: Teruaki Kanzaki, Yoshinori Deguchi, Kazunobu Miki
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Patent number: 8084279Abstract: According to one embodiment of the present invention, a method of manufacturing a semiconductor device includes below steps. A step of preparing a phase shift mask and a normal photomask. A step of stacking a first wiring layer on a semiconductor substrate, and further stacking, on the first wiring layer, a second wiring layer. The second wiring layer includes a second wiring and third wiring. A step of stacking an interlayer insulating film on the second wiring layer. A step of forming, in the interlayer insulating film, a first opening in which the second wiring is exposed, and a second opening in which the third wiring is exposed by photolithography using the normal photomask. A step of burying a metal in the first opening and the second opening. A step of providing a pad to be overlaid on the first and second openings.Type: GrantFiled: March 9, 2010Date of Patent: December 27, 2011Assignee: Renesas Electronics CorporationInventors: Tatsuo Kasaoka, Kiyohiko Sakakibara, Noboru Mori, Kazunobu Miki
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Patent number: 7956473Abstract: Method of manufacturing semiconductor device including forming inter-layer insulating film on semiconductor substrate. First metal film is formed on inter-layer insulating film. First resist is formed on first metal film and patterned. Anisotropic etching performed on first metal film using first resist as mask. First resist is removed and second metal film is formed on inter-layer insulating film to cover remaining first metal film. Second resist is formed on second metal film in area where first metal film exists on inter-layer insulating film and part of area where first metal film does not exist. Anisotropic etching is performed on second metal film using second resist as mask and bonding pad having first metal film and second metal film, and upper layer wiring having second metal film and not first metal film. Second resist is removed. Surface protection film covering bonding pad is formed. Pad opening is formed on bonding pad.Type: GrantFiled: July 23, 2008Date of Patent: June 7, 2011Assignee: Renesas Electronics CorporationInventors: Hiroyuki Momono, Hiroshi Mitsuyama, Katsuhiro Hasegawa, Keiko Nishitsuji, Kazunobu Miki
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Publication number: 20100155960Abstract: The present invention aims at offering the semiconductor device which can improve the strength to the stress generated with a bonding pad. In the semiconductor device concerning the present invention, a plurality of bonding pads are formed on a semiconductor chip. In each bonding pad, a plurality of second line-like metals are formed under the first metal formed using the wiring layer of the top layer. And a bonding pad is put in order and located along the long-side direction of a second metal to achieve the above objects. That is, a bonding pad is put in order and located so that the long-side direction of a second metal and the arrangement direction of a bonding pad may become in the same direction.Type: ApplicationFiled: March 2, 2010Publication date: June 24, 2010Applicant: Renesas Technology CorporationInventors: Teruaki KANZAKI, Yoshinori Deguchi, Kazunobu Miki
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Publication number: 20100159690Abstract: According to one embodiment of the present invention, a method of manufacturing a semiconductor device includes below steps. A step of preparing a phase shift mask and a normal photomask. A step of stacking a first wiring layer on a semiconductor substrate, and further stacking, on the first wiring layer, a second wiring layer. The a second wiring layer includes a second wiring and a third wiring. A step of stacking an interlayer insulating film on the second wiring layer. A step of forming, in the interlayer insulating film, a first opening in which the second wiring is exposed, and a second opening in which the third wiring is exposed by photolithography using the normal photomask. A step of burying a metal in the first opening and the second opening. A step of providing a pad to be overlaid on the first and second openings.Type: ApplicationFiled: March 9, 2010Publication date: June 24, 2010Applicant: RENESAS TECHNOLOGY CORP.Inventors: Tatsuo Kasaoka, Kiyohiko Sakakibara, Noboru Mori, Kazunobu Miki
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Patent number: 7701063Abstract: The present invention aims at offering the semiconductor device which can improve the strength to the stress generated with a bonding pad. In the semiconductor device concerning the present invention, a plurality of bonding pads are formed on a semiconductor chip. In each bonding pad, a plurality of second line-like metals are formed under the first metal formed using the wiring layer of the top layer. And a bonding pad is put in order and located along the long-side direction of a second metal to achieve the above objects. That is, a bonding pad is put in order and located so that the long-side direction of a second metal and the arrangement direction of a bonding pad may become in the same direction.Type: GrantFiled: February 22, 2005Date of Patent: April 20, 2010Assignee: Renesas Technology Corp.Inventors: Teruaki Kanzaki, Yoshinori Deguchi, Kazunobu Miki
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Patent number: 7696081Abstract: According to one embodiment of the present invention, a method of manufacturing a semiconductor device includes below steps. A step of preparing a phase shift mask and a normal photomask. A step of stacking a first wiring layer on a semiconductor substrate, and further stacking, on the first wiring layer, a second wiring layer. The a second wiring layer includes a second wiring and a third wiring. A step of stacking an interlayer insulating film on the second wiring layer. A step of forming, in the interlayer insulating film, a first opening in which the second wiring is exposed, and a second opening in which the third wiring is exposed by photolithography using the normal photomask. A step of burying a metal in the first opening and the second opening. A step of providing a pad to be overlaid on the first and second openings.Type: GrantFiled: January 30, 2008Date of Patent: April 13, 2010Assignee: Renesas Technology Corp.Inventors: Tatsuo Kasaoka, Kiyohiko Sakakibara, Noboru Mori, Kazunobu Miki
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Publication number: 20090026635Abstract: A method of manufacturing a semiconductor device comprises: a step of forming an inter-layer insulating film on a semiconductor substrate; a step of forming a first metal film on the inter-layer insulating film; a step of forming a first resist on the first metal film and patterning the first resist; a step of performing anisotropic etching on the first metal film using the first resist as a mask; a step of removing the first resist; a step of forming a second metal film on the inter-layer insulating film so as to cover the remaining first metal film; a step of forming a second resist on the second metal film in an area where the first metal film exists on the inter-layer insulating film and part of an area where the first metal film does not exist; a step of performing anisotropic etching on the second metal film using the second resist as a mask and forming a bonding pad having the first metal film and the second metal film and an upper layer wiring which has the second metal film, yet not the first metal fType: ApplicationFiled: July 23, 2008Publication date: January 29, 2009Inventors: Hiroyuki MOMONO, Hiroshi Mitsuyama, Katsuhiro Hasegawa, Keiko Nishitsuji, Kazunobu Miki
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Publication number: 20080217786Abstract: According to one embodiment of the present invention, a method of manufacturing a semiconductor device includes below steps. A step of preparing a phase shift mask and a normal photomask. A step of stacking a first wiring layer on a semiconductor substrate, and further stacking, on the first wiring layer, a second wiring layer. The a second wiring layer includes a second wiring and a third wiring. A step of stacking an interlayer insulating film on the second wiring layer. A step of forming, in the interlayer insulating film, a first opening in which the second wiring is exposed, and a second opening in which the third wiring is exposed by photolithography using the normal photomask. A step of burying a metal in the first opening and the second opening. A step of providing a pad to be overlaid on the first and second openings.Type: ApplicationFiled: January 30, 2008Publication date: September 11, 2008Inventors: Tatsuo Kasaoka, Kiyohiko Sakakibara, Noboru Mori, Kazunobu Miki
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Patent number: 7276923Abstract: A semiconductor device test probe having a tip portion for being urged against an electrode pad of an integrated semiconductor device to establish an electrical contact against the electrode pad for testing functions of the semiconductor device. The spherical tip portion has a radius of curvature r expressed by 9t?r?35t where r is the radius of curvature of the spherical surface and t is the thickness of the electrode pad. The tip portion may have a first curved surface substantially positioned in the direction of slippage of the probe when the probe is urged against the electrode pad and slipped relative to the electrode pad and a second curved surface opposite to the first curved surface. The first curved surface has a radius of curvature of from 7 ?m to 30 ?m and larger than that of the second curved surface.Type: GrantFiled: August 18, 2005Date of Patent: October 2, 2007Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Megumi Takemoto, Shigeki Maekawa, Yoshihiro Kashiba, Yoshinori Deguchi, Kazunobu Miki
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Patent number: 7274195Abstract: A semiconductor device test probe having a tip portion for being urged against an electrode pad of an integrated semiconductor device to establish an electrical contact against the electrode pad for testing functions of the semiconductor device. The spherical tip portion has a radius of curvature r expressed by 9t?r?35t, where r is the radius of curvature of the spherical surface and t is the thickness of the electrode pad. The tip portion may have a first curved surface substantially positioned in the direction of slippage of the probe when the probe is urged against the electrode pad and slipped relative to the electrode pad and a second curved surface opposite to the first curved surface. The first curved surface has a radius of curvature of from 7 ?m to 30 ?m and larger than that of the second curved surface.Type: GrantFiled: August 22, 2003Date of Patent: September 25, 2007Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Megumi Takemoto, Shigeki Maekawa, Yoshihiro Kashiba, Yoshinori Deguchi, Kazunobu Miki
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Publication number: 20070182001Abstract: The present invention aims at offering the semiconductor device which can improve the strength to the stress generated with a bonding pad. In the semiconductor device concerning the present invention, a plurality of bonding pads are formed on a semiconductor chip. In each bonding pad, a plurality of second line-like metals are formed under the first metal formed using the wiring layer of the top layer. And a bonding pad is put in order and located along the long-side direction of a second metal to achieve the above objects. That is, a bonding pad is put in order and located so that the long-side direction of a second metal and the arrangement direction of a bonding pad may become in the same direction.Type: ApplicationFiled: February 22, 2005Publication date: August 9, 2007Applicant: RENESAS TECHNOLOGY CORP.Inventors: Teruaki Kanzaki, Yoshinori Deguchi, Kazunobu Miki
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Publication number: 20050189955Abstract: A semiconductor device test probe having a tip portion for being urged against an electrode pad of an integrated semiconductor device to establish an electrical contact against the electrode pad for testing functions of the semiconductor device. The spherical tip portion has a radius of curvature r expressed by 9t?r?35t, where r is the radius of curvature of the spherical surface and t is the thickness of the electrode pad. The tip portion may have a first curved surface substantially positioned in the direction of slippage of the probe when the probe is urged against the electrode pad and slipped relative to the electrode pad and a second curved surface opposite to the first curved surface. The first curved surface has a radius of curvature of from 7 ?m to 30 ?m and larger than that of the second curved surface.Type: ApplicationFiled: August 22, 2003Publication date: September 1, 2005Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Megumi Takemoto, Shigeki Maekawa, Yoshihiro Kashiba, Yoshinori Deguchi, Kazunobu Miki
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Patent number: 6888344Abstract: A test probe for semiconductor devices, the test probe having a tip portion which is pressed against a test pad of a semiconductor device to establish electrical contact between the tip portion and the pad for testing the operation of the semiconductor device, wherein the probe is formed to have a tip shape with an angle of not less than 15 degrees formed at the surface of the pad between a tangential line with respect to a tip face of the probe and the pad surface when the probe is pressed against the pad, the tip shape of the probe having a spherical surface meeting the relationship of: ?=cos?1(1?t/R)?15° where the radius of curvature of the spherical surface is R, the thickness of the pad is t, and the angle formed at the pad surface between the tangential line with respect to the probe tip face and the pad surface when the probe is pressed against the pad is ?, the probe have a flat portion at an end of the tip portion.Type: GrantFiled: November 1, 2002Date of Patent: May 3, 2005Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Shigeki Maekawa, Megumi Takemoto, Kazunobu Miki, Mutsumi Kano, Takahiro Nagata, Yoshihiro Kashiba
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Patent number: 6710615Abstract: In a semiconductor element test apparatus and a method of testing a semiconductor element using the apparatus, a plurality of probe needles are brought into contact with semiconductor elements fabricated on a semiconductor wafer, and a structure is provided for attaching a probe card and a reinforcement member to a probe card hold member. In a plurality of mount positions in which a probe card substrate and a reinforcement member are attached to a probe card hold member, counterbores are formed so as to assume substantially the same depth and shape. Analogous mount structures are realized at a plurality of mount positions by way of the counterbores.Type: GrantFiled: October 10, 2001Date of Patent: March 23, 2004Assignee: Renesas Technology Corp.Inventor: Kazunobu Miki
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Patent number: 6646455Abstract: A test probe for semiconductor devices, the test probe having a tip portion which is pressed against a test pad of a semiconductor device to establish electrical contact between the tip portion and the pad for testing the operation of the semiconductor device, wherein the probe is formed to have a tip shape with an angle of not less than 15 degrees formed at the surface of the pad between a tangential line with respect to a tip face of the probe and the pad surface when the probe is pressed against the pad, the tip shape of the probe having a spherical surface meeting the relationship of: &thgr;=cos−1(1−t/R)≧15° where the radius of curvature of the spherical surface is R, the thickness of the pad is t, and the angle formed at the pad surface between the tangential line with respect to the probe tip face and the pad surface when the probe is pressed against the pad is &thgr;, the probe have a flat portion at an end of the tip portion.Type: GrantFiled: July 24, 1998Date of Patent: November 11, 2003Assignee: Mitsubishi Denki Kabsuhiki KaishaInventors: Shigeki Maekawa, Megumi Takemoto, Kazunobu Miki, Mutsumi Kano, Takahiro Nagata, Yoshihiro Kashiba
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Patent number: 6633176Abstract: A semiconductor device test probe having a tip portion for being urged against an electrode pad of an integrated semiconductor device to establish an electrical contact against the electrode pad for testing functions of the semiconductor device. The spherical tip portion has a radius of curvature r expressed by 8t≦r≦23t, where r is the radius of curvature of the spherical surface and t is the thickness of the electrode pad. The tip portion may have a first curved surface substantially positioned in the direction of slippage of the probe when the probe is urged against the electrode pad and slipped relative to the electrode pad and a second curved surface opposite to the first curved surface. The first curved surface has a radius of curvature of from 7 &mgr;m to 30 &mgr;m and larger than that of the second curved surface.Type: GrantFiled: March 19, 2001Date of Patent: October 14, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Megumi Takemoto, Shigeki Maekawa, Yoshihiro Kashiba, Yoshinori Deguchi, Kazunobu Miki
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Publication number: 20030090280Abstract: A test probe for semiconductor devices, the test probe having a tip portion which is pressed against a test pad of a semiconductor device to establish electrical contact between the tip portion and the pad for testing the operation of the semiconductor device, wherein the probe is formed to have a tip shape with an angle of not less than 15 degrees formed at the surface of the pad between a tangential line with respect to a tip face of the probe and the pad surface when the probe is pressed against the pad, the tip shape of the probe having a spherical surface meeting the relationship of:Type: ApplicationFiled: November 1, 2002Publication date: May 15, 2003Inventors: Shigeki Maekawa, Megumi Takemoto, Kazunobu Miki, Mutsumi Kano, Takahiro Nagata, Yoshihiro Kashiba
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Publication number: 20020149385Abstract: In a semiconductor element test apparatus and a method of testing a semiconductor element using the apparatus, a plurality of probe needles are brought into contact with semiconductor elements fabricated on a semiconductor wafer, and a structure is provided for attaching a probe card and a reinforcement member to a probe card hold member. In a plurality of mount positions in which a probe card substrate and a reinforcement member are attached to a probe card hold member, counterbores are formed so as to assume substantially the same depth and shape. Analogous mount structures are realized at a plurality of mount positions by way of the counterbores.Type: ApplicationFiled: October 10, 2001Publication date: October 17, 2002Applicant: Mitsubishi Denki Kabushiki KaishaInventor: Kazunobu Miki
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Publication number: 20020097060Abstract: A test probe for semiconductor devices, the test probe having a tip portion which is pressed against a test pad of a semiconductor device to establish electrical contact between the tip portion and the pad for testing the operation of the semiconductor device, wherein the probe is formed to have a tip shape with an angle of not less than 15 degrees formed at the surface of the pad between a tangential line with respect to a tip face of the probe and the pad surface when the probe is pressed against the pad, the tip shape of the probe having a spherical surface meeting the relationship of:Type: ApplicationFiled: July 24, 1998Publication date: July 25, 2002Inventors: SHIGEKI MAEKAWA, MEGUMI TAKEMOTO, KAZUNOBU MIKI, MUTSUMI KANO, TAKAHIRO NAGATA, YOSHIHIRO KASHIBA