Abstract: Disclosed herein is a signal processing apparatus including: a first decimation processing section for generating, based on a digital signal in a first form, a digital signal in a second form; a second decimation processing section for generating, based on the digital signal in the second form, a digital signal in a third form; a first signal processing section for processing the digital signal in the third form; an interpolation processing section for converting a digital signal in the third form outputted from the first signal processing section into a digital signal in the second form; a second signal processing section for processing the digital signal in the second form outputted from the first decimation processing section; and a combining section for combining the digital signals in the second form outputted from the interpolation processing section and the second signal processing section.

Abstract: Disclosed herein is a signal processing apparatus including: analog-to-digital conversion means for performing delta sigma modulation of generating a digital signal having a predetermined sampling frequency and a predetermined quantization bit rate of one or more bits based on an input analog signal; signal processing means including a digital filter having a characteristic for outputting a digital signal having a sampling frequency n×Fs (Fs is a reference sampling frequency) and a quantization bit rate of a bits (a is a natural number greater than one) based on the above digital signal; and digital-to-analog conversion means including a part for performing delta sigma modulation for outputting a digital signal having a sampling frequency n×Fs and a quantization bit rate of b bits (b is a natural number greater than zero and less than a) based on a digital signal outputted from the signal processing means.

Abstract: A signal processing apparatus includes first and second extracting units extracting frequency components having a first frequency band and a second frequency band, respectively, from an input audio signal, a first-harmonic-component generating unit generating a first-harmonic-component signal including a frequency component whose frequency is N1 times that of the frequency component extracted in the first extracting unit, a second-harmonic-component generating unit generating a second-harmonic-component signal including a frequency component whose frequency is N2 times that of the frequency component extracted in the second extracting unit, and a combining unit combining the input audio signal, and the first- and the second-harmonic-component signals in a predetermined ratio. The first frequency band is higher than the second frequency band. N1 and N2 are positive integers, and N1 is smaller than N2.

Abstract: An audio signal processing apparatus includes a high-pass filter for extracting from an audio signal a frequency component higher than f0, n band-pass filters for extracting, from the audio signal, frequency components falling within a frequency range from f0/N to f1/N, n harmonic overtone generators for frequency multiplying each of outputs of the n band-pass filters by N, a first combining unit for combining the generated harmonic overtone components, a level detector for detecting a level of a supplied harmonic overtone component, a gain controller for controlling dynamically the harmonic overtone component supplied from the first combining unit, and a second combining unit for combining the frequency component extracted by the high-pass filter and a harmonic overtone component output from the gain controller, where N is (n being a natural number), f0 is a first predetermined frequency, and f1 is a second predetermined frequency higher than f0.

Abstract: Samples of a component having a frequency less than a predetermined frequency in an input audio signal that is a digital signal having a predetermined sampling frequency are written in a memory. A harmonic-overtone signal having a frequency N times a frequency of the input audio signal is generated by repeating an operation N times, where N is an integer more than one, the operation including reading one sample and thinning out (N-1) samples for every N samples from the memory within each cycle period from a first one-direction zero-crossing point to a second one-direction zero-crossing point subsequent to the first one-direction zero-crossing point, each one-direction zero-crossing point being a point at which a level of the input audio signal changes from negative to positive or a point at which the level of the input audio signal changes from positive to negative.

Abstract: A class-D amplifier has a switching amplifying-unit, which includes a pair of switching elements. The unit drives the switching elements and generates pulse amplified switching signals. The amplifier also has a signal-generating unit, which generates pulse width modulation signals each for driving the switching elements and supplies the generated pulse-width modulation signals to the. switching amplifying-unit. The switching amplifying-unit includes a detecting sub-unit, which detects an operating state of the switching elements. The signal-generating unit includes a dead-time-setting sub-unit, which sets dead time relative to the switching elements by delaying each of the pulse width modulation signals using propagation delay times in logic devices. The signal-generating unit also includes a control sub-unit, which controls the dead-time-setting sub-unit based on a detected result of the detecting sub-unit to change the dead time based on the operating state of the switching elements.

Abstract: A D/A converter in which distortion caused by PWM is favorably removed even if a sampling frequency is low relative to a signal frequency is provided. The D/A converter includes a pulse-width-modulated-signal outputting circuit for outputting a pulse-width-modulated signal having a pulse width in accordance with a digital value of an input digital signal.

Abstract: In an audio amplifier having a D-class power amplifier, a noise upon muting is suppressed. A sampling rate converter circuit for sampling rate converting a digital audio signal into a digital audio signal, and a ?? modulation circuit for re-quantizing the digital audio signal into a bit-reduced digital audio signal are provided. Further, a PWM modulation circuit for converting the digital audio signal into a PWM signal, and a D-class power amplifier to which the PWM signal are supplied. Still further, a dither signal forming circuit for superimposing a dither signal SDI on the digital audio signal, and a forming circuit for forming a muting signal SDET are provided. Upon muting, an input side of the sampling rate converter circuit is stopped by the muting signal SDET.

Abstract: A class D power amplifier (1) switches a power supply voltage VDD at high-speed in response to an input digital audio signal Pin to power-amplify the digital audio signal Pin, and supplies a speaker (2) with the amplified signal. In the case of being incorporated in an AM receiver formed integrally with an AM tuner (3) for receiving AM broadcasts, the class D power amplifier (1) can reduces influence of reception interference with respect to the AM tuner (3). As a result, it is possible to provide a power amplifier that can suppress unnecessary radiation to reduce reception interference with respect to the tuner, not by changing a carrier frequency, but by controlling the drive signal generation systems.

Abstract: A class-D amplifier has a switching amplifying-unit, which includes a pair of switching elements. The unit drives the switching elements and generates pulse amplified switching signals. The amplifier also has a signal-generating unit, which generates pulse width modulation signals each for driving the switching elements and supplies the generated pulse-width modulation signals to the switching amplifying-unit. The switching amplifying-unit includes a detecting sub-unit, which detects an operating state of the switching elements. The signal-generating unit includes a dead-time-setting sub-unit, which sets dead time relative to the switching elements by delaying each of the pulse width modulation signals using propagation delay time in logic devices. The signal-generating unit also includes a control sub-unit, which controls the dead-time-setting sub-unit based on a detected result of the detecting sub-unit to change the dead time based on the operating state of the switching elements.

Abstract: In an audio amplifier having a D-class power amplifier, a noise upon muting is suppressed. There are provided a sampling rate converter circuit 23 for sampling rate converting a digital audio signal S11 into a digital audio signal S23, and a ?? modulation circuit 14 for re-quantizing the digital audio signal S23 into a bit-reduced digital audio signal S14. Further, there are provided a PWM modulation circuit 15 for converting the digital audio signal S14 into a PWM signal S15, and a D-class power amplifier 16 to which the PWM signal S15 is supplied. Still further, there are provided a dither signal forming circuit 18 for superimposing a dither signal SDI on the digital audio signal S23, and a forming circuit 19 for forming a muting signal SDET. Upon muting, an input side of the sampling rate converter circuit 23 is stopped by the muting signal SDET.

Abstract: A remote control device is configured so that a display direction of contents on a liquid crystal display section can be switched according to slide operation of a slide switch. The remote control device can prevent the display direction from being switched despite the intention of a user, thus more appropriately switching the display direction of contents displayed on the liquid crystal display section.

Abstract: A sampling frequency conversion apparatus which easily controls the phase difference (time difference) between the input data and the output data in converting the sampling frequency, includes a storage device 13 for continuously writing the input data or the data obtained by over-sampling the input data and for continuously reading out the data written maintaining a predetermined address difference relative to the writable address, and an interpolation processing unit 14 for interpolating the data read-out from the storage device 13 to obtain data of which the sampling frequency is converted. In converting the sampling frequency, an address difference between a writable address and a readable address in the storage device 13 is optimized, the address difference being optimized without limitation for a predetermined period of time from the start of supplying the input data and, then, being optimized by imposing a predetermined limitation after the passage of the predetermined period of time.

Abstract: A sampling frequency conversion apparatus which easily controls the phase difference (time difference) between the input data and the output data in converting the sampling frequency, and comprises storage means 13 for continuously writing the input data or the data obtained by over-sampling the input data and for continuously reading out the data written maintaining a predetermined address difference relative to the write address, and interpolation processing means 14 for interpolating the data read out from the storage means 13 to obtain data of which the sampling frequency is converted. In converting the sampling frequency, an address difference between a write address and a read address in the storage means 13 is optimized, the address difference being optimized without limitation for a predetermined period of time from the start of supplying the input data and, then, being optimized by imposing a predetermined limitation after the passage of the predetermined period of time.

Abstract: A class D power amplifier (1) switches a power supply voltage VDD at high-speed in response to an input digital audio signal Pin to power-amplify the digital audio signal Pin, and supplies a speaker (2) with the amplified signal. In the case of being incorporated in an AM receiver formed integrally with an AM tuner (3) for receiving AM broadcasts, the class D power amplifier (1) can reduces influence of reception interference with respect to the AM tuner (3). As a result, it is possible to provide a power amplifier that can suppress unnecessary radiation to reduce reception interference with respect to the tuner, not by changing a carrier frequency, but by controlling the drive signal generation systems.

Abstract: A power amplifier for reducing emission generated at the edges of output voltages. A pair of PWM modulation circuits (11) and (12) to which an input signal is sent; a pair of push-pull circuits (15) and (16); and drive circuits (13) and (14) for sending the outputs of the PWM modulation circuits (11) and (12) as drive signals to the push-pull circuits (15) and (16) are provided. A speaker (19) is connected between the output end of the push-pull circuit (15) and the output end of the push-pull circuit (16). The drive circuits (13) and (14) are switched at intervals equal to the cycle period of pulse modulation signals such that the drive signals sent to the push-pull circuits (15) and (16) are not changed at the end points of each cycle period of the pulse modulation signals.

Abstract: A power amplifier for reducing emission generated at the edges of output voltages. A pair of PWM modulation circuits (11) and (12) to which an input signal is sent; a pair of push-pull circuits (15) and (16); and drive circuits (13) and (14) for sending the outputs of the PWM modulation circuits (11) and (12) as drive signals to the push-pull circuits (15) and (16) are provided. A speaker (19) is connected between the output end of the push-pull circuit (15) and the output end of the push-pull circuit (16). The drive circuits (13) and (14) are switched at intervals equal to the cycle period of pulse modulation signals such that the drive signals sent to the push-pull circuits (15) and (16) are not changed at the end points of each cycle period of the pulse modulation signals.

Abstract: A signal amplifier apparatus adapted for carrying out delta-sigma modulation of an input signal to carry out pulse width modulation (PWM) of that signal, to obtain a PWM signal, and to amplify this PWM signal so that a signal of a predetermined magnitude is obtained, wherein the signal amplifier apparatus includes a correction circuit for correcting an output of a quantizer provided in a delta-sigma modulation device. The correction circuit is installed in a feedback path with respect to the input side from the quantizer or immediately before a pulse width modulator to thereby correct distortion taking place in the amplifier. In addition, the signal amplifier apparatus invention compares PWM signals at the input and the output of the amplifier to correct the output of the quantizer that is provided in the delta-sigma modulation device, so as to cancel distortion taking place in the amplifier in accordance with respective rising time difference and falling time difference to thereby correct distortion.

Abstract: A power amplifier circuit includes a pair of PWM circuits, to which an input signal is supplied, a pair of push-pull circuits, and drive circuits for supplying the outputs of the PWM circuits to the push-pull circuits as drive signals. A speaker is arranged between the output end of one push-pull circuit and the output end of the other push-pull circuit. The drive circuits alternately drive the respective push-pull circuits every cycle time of a PWM signal. The circuit can suppress radiation caused by the variation in output voltages.

Abstract: A D/A converter in which distortion caused by PWM is favorably removed even if a sampling frequency is low relative to a signal frequency is provided. The D/A converter includes a pulse-width-modulated-signal outputting circuit for outputting a pulse-width-modulated signal having a pulse width in accordance with a digital value of an input digital signal.