Abstract: A system, e.g., a system on a chip (SoC) includes a first domain including a first processor configured to boot the system; a second domain including a processing subsystem having a second processor; and isolation circuitry between the first domain and the second domain During boot-up of the system, the first processor provides code to the second domain. When the code is executed by the second processor, it configures the processing subsystem as either a safety domain or as a general-purpose processing domain. The safety domain may an external safety domain or an internal safety domain.

Abstract: A system on a chip (SoC) includes a first domain comprising a first processor configured to boot the SoC, and a first debug subsystem, a second domain comprising a second processor, the second domain configurable as either a safety domain or a general-purpose processing domain, and isolation circuitry between the first domain and the second domain. During boot-up of the SoC, the first processor provides code to the second domain which, when executed by the second processor, configures the second domain as either a safety domain or as a general-purpose processing domain.

Abstract: In described examples, an integrated circuit (IC) includes an isolation, an input/output (IO), and a low power mode (LPM) control logic. The isolation includes a level shift with pull-down configured to weakly pull down the voltage of signals that travel through the isolation. The IO includes an input and a physical connector for coupling to a power management IC. The IO provides an asserted-low LPM enable signal to the physical connector in response to the IO input. An output of the LPM control logic is coupled via the isolation to the input of the IO. The LPM control logic provides a high voltage signal to the input of the IO as a default during power on reset (POR) of the IC. The pull-down pulls the LPM enable signal voltage to the asserted low voltage in response to a voltage of the LPM enable signal falling below a threshold.

Abstract: A system on a chip (SoC) includes a first domain comprising a first processor configured to boot the SoC, and a first debug subsystem, a second domain comprising a second processor, the second domain configurable as either a safety domain or a general-purpose processing domain, and isolation circuitry between the first domain and the second domain. During boot-up of the SoC, the first processor provides code to the second domain which, when executed by the second processor, configures the second domain as either a safety domain or as a general-purpose processing domain.

Abstract: A circuit device is provided and includes a first power domain comprising a universal serial bus (USB) subsystem and/or a memory controller subsystem. The first power domain is configured to isolate the USB subsystem and/or the memory controller subsystem from a power-on-reset signal asserted during a low power mode.

Abstract: A system having multiple power mode types, for example, includes a power manager that is responsive to a selection of a suspend power mode type for maintaining processor context information in volatile memory while the processor is in the selected suspend mode. A status register is arranged to retain the status of the context information in the volatile memory while the processor is in the selected suspend power mode. The power manager is arranged to selectively apply power to various voltage domains in response to the type of power mode selected. The processor is optionally arranged to signal the power manager of transitions to the selected suspend mode and of transitions to an active mode using a power enable signal.

Abstract: A system having multiple power mode types, for example, includes a power manager that is responsive to a selection of a suspend power mode type for maintaining processor context information in volatile memory while the processor is in the selected suspend mode. A status register is arranged to retain the status of the context information in the volatile memory while the processor is in the selected suspend power mode. The power manager is arranged to selectively apply power to various voltage domains in response to the type of power mode selected. The processor is optionally arranged to signal the power manager of transitions to the selected suspend mode and of transitions to an active mode using a power enable signal.

Abstract: An information terminal that can perform image processing in consonance with the use state and the use purpose. When a retrial module is started, removal means removes part or all of the interpolation processing performed for a Bayer-type module. Thereafter, data obtained by the removal are transmitted to color interpolation means, another color interpolation process is performed for the data, and the resultant data are transmitted to image quality correction means. The image quality correction means performs another image quality correction process for the data, and transmits the obtained data to JPEG encoding means.

Abstract: This invention samples and transmits the CEA-909 standard smart antenna analog pulse train waveforms using only a digital I/O pin for both mode A and mode B operation. This invention implements the smart antenna interface based on a single digital programmable counter. This counter is programmable so that it can tolerate or produce wide variation of symbol width.

Abstract: A camera module chip-set comprising: a decompressor configured to decompress image data received from a host device connected to the camera module chip-set; and a processor, different to the decompressor, configured to control transmission of the decompressed image data to the connected host device, in order for the decompressed image data to be displayed on a display of the host device.

Abstract: An image processing apparatus for processing pieces of color image data each including a plurality of sub-pieces of color image data pertaining to the plurality of color components respectively comprises: initial color image inputting means; data dividing means responsive to the initial color image data for dividing it in respect of color components and for providing pieces of mono-color image data each corresponding to one of the sub-pieces of color image data of the piece of initial color image data, the number of the pieces of mono-color image data being equal to or larger than the number of the color components; data processing means for effecting a predetermined processing on each piece of mono-color image data to provide secondary image data; and secondary image data outputting means.

Abstract: This device includes an image data creator that creates a first type of image data for test shooting and creating a second type of image data for real shooting; a compressor that compresses the image data in a predetermined compression format; and a processor; wherein the compressor has one or plural compression parameters relating to a compression rate; the creator newly supplies files of the first type to the compressor one after another; the compressor compresses at least two files among the continuously supplied first type using values of compression parameters; the processor decides the value of the compression parameter to be used for the second type according to a predetermined standard, based on two and more files of first type image data that are compressed using values of compression parameters; and the processor sets the value of the compression parameter of the compressor at the decided value.

Abstract: This invention samples and transmits the CEA-909 standard smart antenna analog pulse train waveforms using only a digital I/O pin for both mode A and mode B operation. This invention implements the smart antenna interface based on a single digital programmable counter. This counter is programmable so that it can tolerate or produce wide variation of symbol width.

Abstract: This device includes a camera, a host module, an interface part, and a chassis, wherein the host module has a host CPU that is connected to the interface, the camera module has a register that is provided with a first area and a second area distinguished from the first area depending on the address, and a camera CPU that receives the interruption when the data is written in the first area, the host CPU prepares a type of data and writes it in the first area, the camera CPU prepares dual data that correspond to the written type of data and writes it in the second area, and the host CPU can directly read the data from the second area while designating the address of the second area and further, the host CPU can directly write the data in the second area while designating the address of the second area.

Abstract: This device includes a camera, a host module, an interface part, and a chassis, wherein the host module has a host CPU that is connected to the interface, the camera module has a resister that is provided with a first area and a second area distinguished from the first area depending on the address, and a camera CPU that receives the interruption when the data is written in the first area, the host CPU prepares a type of data and writes it in the first area, the camera CPU prepares dual data that correspond to the written type of data and writes it in the second area, and the host CPU can directly read the data from the second area while designating the address of the second area and further, the host CPU can directly write the data in the second area while designating the address of the second area.

Abstract: A mobile camera telephone including a camera module for capturing an image and providing digital data in an RGB format; and an application processor including a CPU for controlling the operation of the telephone and hardware arranged to perform camera image processing on the digital data in RGB format received from the camera module. A method of recording an image using a mobile camera telephone comprising the steps of capturing an image in a first camera component of the mobile camera telephone sending digital data in an RGB format from the first component to a second application processing component of the mobile camera telephone; and, in the application processing component, both image processing the digital data in RGB format to produce an image for viewing and controlling the storage of that image in the telephone.

Abstract: This device includes an image data creator that creates a first type of image data for test shooting and creating a second type of image data for real shooting; a compressor that compresses the image data in a predetermined compression format; and a processor; wherein the compressor has one or plural compression parameters relating to a compression rate; the creator newly supplies files of the first type to the compressor one after another; the compressor compresses at least two files among the continuously supplied first type using values of compression parameters; the processor decides the value of the compression parameter to be used for the second type according to a predetermined standard, based on two and more files of first type image data that are compressed using values of compression parameters; and the processor sets the value of the compression parameter of the compressor at the decided value.

Abstract: An information terminal that can perform image processing in consonance with the use state and the use purpose. When a retrial module is started, removal means removes part or all of the interpolation processing performed for a Bayer-type module. Thereafter, data obtained by the removal are transmitted to color interpolation means, another color interpolation process is performed for the data, and the resultant data are transmitted to image quality correction means. The image quality correction means performs another image quality correction process for the data, and transmits the obtained data to JPEG encoding means.

Abstract: A digital camera system is formed from a host device and a camera module. The host device has a user interface for receiving user input that controls the operation of a connected camera module and a first processor operable in response to user input via the user interface specifying a camera action, to create a request message. The camera module has image capturing means and a second processor operable to decode a request message to control the image capturing means. When the camera module is attached to the host device the first and second processors are connected for communication.

Abstract: An image processing apparatus for processing pieces of color image data each including a plurality of sub-pieces of color image data pertaining to the plurality of color components respectively comprises: initial color image inputting means; data dividing means responsive to the initial color image data for dividing it in respect of color components and for providing pieces of mono-color image data each corresponding to one of the sub-pieces of color image data of the piece of initial color image data, the number of the pieces of mono-color image data being equal to or larger than the number of the color components; data processing means for effecting a predetermined processing on each piece of mono-color image data to provide secondary image data; and secondary image data outputting means.