Abstract: A stabilized regulator circuit is provided A first Pch transistor (PTr) (P1) whose source is connected to a power supply line and whose drain is connected to an output terminal that outputs a load current, a PTr (P2) whose source and gate are respectively connected to the source and gate of the PTr (P1), resistor elements connected in series between the output terminal and ground, a resistor element (R3) connected between a drain of P2 and ground, and an amplifier which controls P1 and P2 based on a difference between potential of a connection point of the resistor elements and a reference. A comparator, with a differential amplifier input stage configured by an Nch transistor, compares potential difference between two ends of R3 and potential difference between the connection point of the resistor elements and ground, and when the former is larger, controls P1 so as to limit load current.

Abstract: In a hysteresis characteristic input circuit, first and second resistors are connected in parallel between a first power supply terminal and a connection point, and first and second MOS transistors are connected in parallel between the connection point and a second power supply terminal and are controlled by an input voltage. An inverter has an input connected to the connection point and an output adapted to generate an output voltage. A first switching element is connected in series to the second resistor, and a second switching element is connected in series to the second MOS transistor. The first and second switching elements are complementarily controlled by the output voltage.

Abstract: A stabilized regulator circuit is provided A first Pch transistor (PTr) (P1) whose source is connected to a power supply line and whose drain is connected to an output terminal that outputs a load current, a PTr (P2) whose source and gate are respectively connected to the source and gate of the PTr (P1), resistor elements connected in series between the output terminal and ground, a resistor element (R3) connected between a drain of P2 and ground, and an amplifier which controls P1 and P2 based on a difference between potential of a connection point of the resistor elements and a reference. A comparator, with a differential amplifier input stage configured by an Nch transistor, compares potential difference between two ends of R3 and potential difference between the connection point of the resistor elements and ground, and when the former is larger, controls P1 so as to limit load current.

Abstract: A charge pump circuit is provided with a capacitor for generating a boosted voltage from a power supply voltage in response to a clock signal; and an output node from which the boosted voltage is externally outputted. The capacitor includes a first well formed within a substrate, a second well formed within the first well, first and second diffusion regions formed within the second well to receive the clock signal, a channel region provided between the first and second diffusion regions in which channel region a channel is formed in response to the clock signal; and an electrode positioned over the channel region across a dielectric and connected with the output node. The output node is also connected with the first well to apply said boosted voltage to the first well.

Abstract: In a hysteresis characteristic input circuit, first and second resistors are connected in parallel between a first power supply terminal and a connection point, and first and second MOS transistors are connected in parallel between the connection point and a second power supply terminal and are controlled by an input voltage. An inverter has an input connected to the connection point and an output adapted to generate an output voltage. A first switching element is connected in series to the second resistor, and a second switching element is connected in series to the second MOS transistor. The first and second switching elements are complementarily controlled by the output voltage.

Abstract: A charge pump circuit is provided with a capacitor for generating a boosted voltage from a power supply voltage in response to a clock signal; and an output node from which the boosted voltage is externally outputted. The capacitor includes a first well formed within a substrate, a second well formed within the first well, first and second diffusion regions formed within the second well to receive the clock signal, a channel region provided between the first and second diffusion regions in which channel region a channel is formed in response to the clock signal; and an electrode positioned over the channel region across a dielectric and connected with the output node. The output node is also connected with the first well to apply said boosted voltage to the first well.