Patents by Inventor Kazunori Hara

Kazunori Hara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130014981
    Abstract: An electromagnetic wave propagation apparatus includes: a planar propagation medium including a planar conductor, a first planar dielectric, a planar mesh conductor, and a second planar dielectric being overlaid on each other in order; at least one electromagnetic wave input port provided for the planar propagation medium; a power supply station that supplies the planar propagation medium with an electromagnetic wave as electric power or information through the electromagnetic wave input port; and at least one power receiving apparatus provided for a second planar dielectric of the planar propagation medium and includes an electromagnetic wave interface and a power receiving circuit. A dielectric board is provided with multiple conductor patterns as the electromagnetic wave interface. At least one connection means is provided between the conductor pattern and the power receiving circuit. At least one short-circuit means between the conductor patterns is provided at an end of the conductor pattern.
    Type: Application
    Filed: July 12, 2012
    Publication date: January 17, 2013
    Inventors: Hiroshi SHINODA, Takahide TERADA, Kazunori HARA
  • Patent number: 8111340
    Abstract: A display apparatus includes scanning lines; signal lines crossing the scanning lines; thin-film transistors connected to the scanning lines and the signal lines; capacitors connected to the thin-film transistors; interlayer insulating films disposed over the scanning lines with the signal lines, the thin-film transistors, and the capacitors disposed between or on the interlayer insulating films; upper interlayer insulating films disposed above the signal lines, the thin-film transistors, and the capacitors; common lines disposed between or on the upper interlayer insulating films; pixel electrodes disposed between or on the upper interlayer insulating films; and connection holes continuously penetrating the interlayer insulating films disposed between the common lines and the capacitors. The common lines and the capacitors are directly connected via the connection holes, and the connection holes have a ratio of depth to opening width of more than 1.
    Type: Grant
    Filed: September 4, 2007
    Date of Patent: February 7, 2012
    Assignee: Sony Corporation
    Inventors: Kazuyoshi Yamashita, Yuichi Yamaguchi, Kazunori Hara
  • Publication number: 20080067570
    Abstract: A display apparatus includes scanning lines; signal lines crossing the scanning lines; thin-film transistors connected to the scanning lines and the signal lines; capacitors connected to the thin-film transistors; interlayer insulating films disposed over the scanning lines with the signal lines, the thin-film transistors, and the capacitors disposed between or on the interlayer insulating films; upper interlayer insulating films disposed above the signal lines, the thin-film transistors, and the capacitors; common lines disposed between or on the upper interlayer insulating films; pixel electrodes disposed between or on the upper interlayer insulating films; and connection holes continuously penetrating the interlayer insulating films disposed between the common lines and the capacitors. The common lines and the capacitors are directly connected via the connection holes, and the connection holes have a ratio of depth to opening width of more than 1.
    Type: Application
    Filed: September 4, 2007
    Publication date: March 20, 2008
    Applicant: SONY CORPORATION
    Inventors: Kazuyoshi Yamashita, Yuichi Yamaguchi, Kazunori Hara