Patents by Inventor Kazunori Hasegawa

Kazunori Hasegawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240281177
    Abstract: A printing system includes: a driver that accepts a user operation related to setting of a print job and provides an instruction related to the print job; a printing unit that performs cover/interleaving paper printing in which printing is performed with at least a cover or an interleaving paper inserted, on the basis of the instruction; a booklet creating unit that performs booklet creation processing of creating a booklet by center-folding the cover and sandwiching other center-folding printed papers, on the basis of the instruction; and a pre-processing unit that performs processing of making a linear bending mark or a folding mark as pre-processing at a position on the cover, before the center-folding, at which the center-folding is to be performed, on the basis of the instruction.
    Type: Application
    Filed: January 4, 2024
    Publication date: August 22, 2024
    Inventor: Kazunori HASEGAWA
  • Publication number: 20240069836
    Abstract: An image forming system includes a plurality of image forming apparatuses and an information processing apparatus, and the plurality of image forming apparatuses include a parent apparatus and a child apparatus(es). The parent apparatus transmits, when receiving a print instruction that is transmitted from the child apparatus for outputting operated by a user, print data to the child apparatus for outputting. The parent apparatus transmits, when transmission instruction data is included in the print data, print image data included in the print data to a transmission destination apparatus such as a child apparatus other than the child apparatus for outputting, the information processing apparatus and a further external apparatus with which the parent apparatus can perform communication via a network.
    Type: Application
    Filed: November 9, 2023
    Publication date: February 29, 2024
    Inventors: Kazunori Hasegawa, Satoshi Awata
  • Patent number: 11847370
    Abstract: An image forming system includes a plurality of image forming apparatuses and an information processing apparatus, and the plurality of image forming apparatuses include a parent apparatus and a child apparatus(es). The parent apparatus transmits, when receiving a print instruction that is transmitted from the child apparatus for outputting operated by a user, print data to the child apparatus for outputting. The parent apparatus transmits, when transmission instruction data is included in the print data, print image data included in the print data to a transmission destination apparatus such as a child apparatus other than the child apparatus for outputting, the information processing apparatus and a further external apparatus with which the parent apparatus can perform communication via a network.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: December 19, 2023
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Kazunori Hasegawa, Satoshi Awata
  • Publication number: 20220357898
    Abstract: An image forming system includes a plurality of image forming apparatuses and an information processing apparatus, and the plurality of image forming apparatuses include a parent apparatus and a child apparatus(es). The parent apparatus transmits, when receiving a print instruction that is transmitted from the child apparatus for outputting operated by a user, print data to the child apparatus for outputting. The parent apparatus transmits, when transmission instruction data is included in the print data, print image data included in the print data to a transmission destination apparatus such as a child apparatus other than the child apparatus for outputting, the information processing apparatus and a further external apparatus with which the parent apparatus can perform communication via a network.
    Type: Application
    Filed: July 25, 2022
    Publication date: November 10, 2022
    Inventors: Kazunori HASEGAWA, SATOSHI AWATA
  • Patent number: 11444010
    Abstract: A semiconductor device includes: a semiconductor chip including a field effect transistor for switching; a die pad on which the semiconductor chip is mounted via a first bonding material; a lead electrically connected to a pad for source of the semiconductor chip through a metal plate; a lead coupling portion formed integrally with the lead; and a sealing portion for sealing them. A back surface electrode for drain of the semiconductor chip and the die pad are bonded via the first bonding material, the metal plate and the pad for source of the semiconductor chip are bonded via a second bonding material, and the metal plate and the lead coupling portion are bonded via a third bonding material. The first, second, and third bonding materials have conductivity, and an elastic modulus of each of the first and second bonding materials is lower than that of the third bonding material.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: September 13, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kazunori Hasegawa, Yuichi Yato, Hiroyuki Nakamura, Yukihiro Sato, Hiroya Shimoyama
  • Patent number: 11435967
    Abstract: An image forming system includes a plurality of image forming apparatuses and an information processing apparatus, and the plurality of image forming apparatuses include a parent apparatus and a child apparatus(es). The parent apparatus transmits, when receiving a print instruction that is transmitted from the child apparatus for outputting operated by a user, print data to the child apparatus for outputting. The parent apparatus transmits, when transmission instruction data is included in the print data, print image data included in the print data to a transmission destination apparatus such as a child apparatus other than the child apparatus for outputting, the information processing apparatus and a further external apparatus with which the parent apparatus can perform communication via a network.
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: September 6, 2022
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Kazunori Hasegawa, Satoshi Awata
  • Publication number: 20220066709
    Abstract: An image forming system includes a plurality of image forming apparatuses and an information processing apparatus, and the plurality of image forming apparatuses include a parent apparatus and a child apparatus(es). The parent apparatus transmits, when receiving a print instruction that is transmitted from the child apparatus for outputting operated by a user, print data to the child apparatus for outputting. The parent apparatus transmits, when transmission instruction data is included in the print data, print image data included in the print data to a transmission destination apparatus such as a child apparatus other than the child apparatus for outputting, the information processing apparatus and a further external apparatus with which the parent apparatus can perform communication via a network.
    Type: Application
    Filed: August 25, 2021
    Publication date: March 3, 2022
    Inventors: Kazunori HASEGAWA, SATOSHI AWATA
  • Publication number: 20210118781
    Abstract: A semiconductor device includes: a semiconductor chip including a field effect transistor for switching; a die pad on which the semiconductor chip is mounted via a first bonding material; a lead electrically connected to a pad for source of the semiconductor chip through a metal plate; a lead coupling portion formed integrally with the lead; and a sealing portion for sealing them. A back surface electrode for drain of the semiconductor chip and the die pad are bonded via the first bonding material, the metal plate and the pad for source of the semiconductor chip are bonded via a second bonding material, and the metal plate and the lead coupling portion are bonded via a third bonding material. The first, second, and third bonding materials have conductivity, and an elastic modulus of each of the first and second bonding materials is lower than that of the third bonding material.
    Type: Application
    Filed: October 1, 2020
    Publication date: April 22, 2021
    Inventors: Kazunori HASEGAWA, Yuichi YATO, Hiroyuki NAKAMURA, Yukihiro SATO, Hiroya SHIMOYAMA
  • Patent number: 10298242
    Abstract: A phase control oscillator includes a voltage control oscillator, a phase comparator, a loop filter, and a storage unit. The loop filter is configured such that if the phase control oscillator starts operating, the loop filter outputs a control voltage based on phase difference information to the voltage control oscillator. The storage unit stores deviation information indicative of a deviation between a phase difference when the loop filter outputs the control voltage in the case where the phase control oscillator starts operating and the phase difference indicated by the phase difference information. After the loop filter outputs the control voltage in response to the phase control oscillator starting operating, the loop filter outputs the control voltage based on the phase difference information output from the phase comparator and the deviation information stored in the storage unit, to the voltage control oscillator.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: May 21, 2019
    Assignee: NIHON DEMPA KOGYO CO., LTD.
    Inventors: Ken Miyahara, Kazunori Hasegawa
  • Patent number: 10262927
    Abstract: Reliability of a semiconductor device is improved. For this, embodied is a basic idea that a semiconductor chip (CHP1) mounted on an Ag layer (AGL) is fixed by using a temporarily fixing material (TA) having tackiness without forming the temporarily fixing material (TA) on a surface of the Ag layer (AGL) having a porous structure as much as possible, is realized. More specifically, the temporarily fixing material (TA) is supplied so as to have a portion made in contact with a chip mounting part (TAB), and the semiconductor chip (CHP1) is also mounted on the Ag layer (AGL) so that one portion of a rear surface of the semiconductor chip (CHP1) is made in contact with the temporarily fixing material (TA).
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: April 16, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kazunori Hasegawa, Hiroi Oka
  • Publication number: 20180269883
    Abstract: A phase control oscillator includes a voltage control oscillator, a phase comparator, a loop filter, and a storage unit. The loop filter is configured such that if the phase control oscillator starts operating, the loop filter outputs a control voltage based on phase difference information to the voltage control oscillator. The storage unit stores deviation information indicative of a deviation between a phase difference when the loop filter outputs the control voltage in the case where the phase control oscillator starts operating and the phase difference indicated by the phase difference information. After the loop filter outputs the control voltage in response to the phase control oscillator starting operating, the loop filter outputs the control voltage based on the phase difference information output from the phase comparator and the deviation information stored in the storage unit, to the voltage control oscillator.
    Type: Application
    Filed: March 13, 2018
    Publication date: September 20, 2018
    Applicant: NIHON DEMPA KOGYO CO., LTD.
    Inventors: Ken MIYAHARA, Kazunori HASEGAWA
  • Publication number: 20180247884
    Abstract: Reliability of a semiconductor device is improved. For this, embodied is a basic idea that a semiconductor chip (CHP1) mounted on an Ag layer (AGL) is fixed by using a temporarily fixing material (TA) having tackiness without forming the temporarily fixing material (TA) on a surface of the Ag layer (AGL) having a porous structure as much as possible, is realized. More specifically, the temporarily fixing material (TA) is supplied so as to have a portion made in contact with a chip mounting part (TAB), and the semiconductor chip (CHP1) is also mounted on the Ag layer (AGL) so that one portion of a rear surface of the semiconductor chip (CHP1) is made in contact with the temporarily fixing material (TA).
    Type: Application
    Filed: July 23, 2015
    Publication date: August 30, 2018
    Inventors: Kazunori HASEGAWA, Hiroi OKA
  • Patent number: 9818678
    Abstract: To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W1 and a narrow part (a second portion) with a second width W2. When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.
    Type: Grant
    Filed: March 23, 2014
    Date of Patent: November 14, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Jumpei Konno, Takafumi Nishita, Nobuhiro Kinoshita, Kazunori Hasegawa, Michiaki Sugiyama
  • Patent number: 9455240
    Abstract: Reliability of a semiconductor device is improved. Each of a plurality of terminals formed on a chip mounting surface included in a wiring substrate has a shape in which a narrow width portion is arranged between adjacent wide width portions in plan view. Moreover, a center of a tip end surface of each of a plurality of protruding electrodes formed on a semiconductor chip mounted on the wiring substrate is arranged at a position where it overlaps the narrow width portion in plan view, and the plurality of terminals and the plurality of protruding electrodes are electrically connected to each other via a solder member.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: September 27, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Jumpei Konno, Takafumi Nishita, Nobuhiro Kinoshita, Kazunori Hasegawa, Michiaki Sugiyama
  • Publication number: 20140320110
    Abstract: A measuring apparatus for measuring a characteristic of a crystal unit includes an input unit, a measuring unit, a storage unit, and a calibrating unit. The input unit is configured to input a measurement signal into the crystal unit. The measuring unit is configured to measure the characteristic of the crystal unit based on an output signal output from the crystal unit with respect to the measurement signal. The storage unit is configured to associate calibration data with a measuring condition to measure the characteristic of the crystal unit, and store the associated data. The calibration data is generated based on a measurement result measured by the measuring unit with connecting a short-circuit element instead of the crystal unit. The calibrating unit is configured to calibrate the characteristic of the crystal unit measured by the measuring unit based on the calibration data.
    Type: Application
    Filed: April 22, 2014
    Publication date: October 30, 2014
    Applicant: NIHON DEMPA KOGYO CO., LTD.
    Inventors: HIROKI MATSUI, KAZUNORI HASEGAWA
  • Publication number: 20140203431
    Abstract: To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W1 and a narrow part (a second portion) with a second width W2. When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.
    Type: Application
    Filed: March 23, 2014
    Publication date: July 24, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Jumpei KONNO, Takafumi NISHITA, Nobuhiro KINOSHITA, Kazunori HASEGAWA, Michiaki SUGIYAMA
  • Publication number: 20140183759
    Abstract: Reliability of a semiconductor device is improved. Each of a plurality of terminals formed on a chip mounting surface included in a wiring substrate has a shape in which a narrow width portion is arranged between adjacent wide width portions in plan view. Moreover, a center of a tip end surface of each of a plurality of protruding electrodes formed on a semiconductor chip mounted on the wiring substrate is arranged at a position where it overlaps the narrow width portion in plan view, and the plurality of terminals and the plurality of protruding electrodes are electrically connected to each other via a solder member.
    Type: Application
    Filed: December 23, 2013
    Publication date: July 3, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Jumpei Konno, Takafumi Nishita, Nobuhiro Kinoshita, Kazunori Hasegawa, Michiaki Sugiyama
  • Patent number: 8701972
    Abstract: To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W1 and a narrow part (a second portion) with a second width W2. When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: April 22, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Takafumi Nishita, Nobuhiro Kinoshita, Jumpei Konno, Michiaki Sugiyama, Kazunori Hasegawa
  • Publication number: 20140004661
    Abstract: To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W1 and a narrow part (a second portion) with a second width W2. When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.
    Type: Application
    Filed: August 29, 2013
    Publication date: January 2, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Jumpei KONNO, Takafumi NISHITA, Nobuhiro KINOSHITA, Kazunori HASEGAWA, Michiaki SUGIYAMA
  • Patent number: 8534532
    Abstract: To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W1 and a narrow part (a second portion) with a second width W2. When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.
    Type: Grant
    Filed: June 24, 2012
    Date of Patent: September 17, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Jumpei Konno, Takafumi Nishita, Nobuhiro Kinoshita, Kazunori Hasegawa, Michiaki Sugiyama