Patents by Inventor Kazunori Hasegawa
Kazunori Hasegawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240281177Abstract: A printing system includes: a driver that accepts a user operation related to setting of a print job and provides an instruction related to the print job; a printing unit that performs cover/interleaving paper printing in which printing is performed with at least a cover or an interleaving paper inserted, on the basis of the instruction; a booklet creating unit that performs booklet creation processing of creating a booklet by center-folding the cover and sandwiching other center-folding printed papers, on the basis of the instruction; and a pre-processing unit that performs processing of making a linear bending mark or a folding mark as pre-processing at a position on the cover, before the center-folding, at which the center-folding is to be performed, on the basis of the instruction.Type: ApplicationFiled: January 4, 2024Publication date: August 22, 2024Inventor: Kazunori HASEGAWA
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Publication number: 20240069836Abstract: An image forming system includes a plurality of image forming apparatuses and an information processing apparatus, and the plurality of image forming apparatuses include a parent apparatus and a child apparatus(es). The parent apparatus transmits, when receiving a print instruction that is transmitted from the child apparatus for outputting operated by a user, print data to the child apparatus for outputting. The parent apparatus transmits, when transmission instruction data is included in the print data, print image data included in the print data to a transmission destination apparatus such as a child apparatus other than the child apparatus for outputting, the information processing apparatus and a further external apparatus with which the parent apparatus can perform communication via a network.Type: ApplicationFiled: November 9, 2023Publication date: February 29, 2024Inventors: Kazunori Hasegawa, Satoshi Awata
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Patent number: 11847370Abstract: An image forming system includes a plurality of image forming apparatuses and an information processing apparatus, and the plurality of image forming apparatuses include a parent apparatus and a child apparatus(es). The parent apparatus transmits, when receiving a print instruction that is transmitted from the child apparatus for outputting operated by a user, print data to the child apparatus for outputting. The parent apparatus transmits, when transmission instruction data is included in the print data, print image data included in the print data to a transmission destination apparatus such as a child apparatus other than the child apparatus for outputting, the information processing apparatus and a further external apparatus with which the parent apparatus can perform communication via a network.Type: GrantFiled: July 25, 2022Date of Patent: December 19, 2023Assignee: SHARP KABUSHIKI KAISHAInventors: Kazunori Hasegawa, Satoshi Awata
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Publication number: 20220357898Abstract: An image forming system includes a plurality of image forming apparatuses and an information processing apparatus, and the plurality of image forming apparatuses include a parent apparatus and a child apparatus(es). The parent apparatus transmits, when receiving a print instruction that is transmitted from the child apparatus for outputting operated by a user, print data to the child apparatus for outputting. The parent apparatus transmits, when transmission instruction data is included in the print data, print image data included in the print data to a transmission destination apparatus such as a child apparatus other than the child apparatus for outputting, the information processing apparatus and a further external apparatus with which the parent apparatus can perform communication via a network.Type: ApplicationFiled: July 25, 2022Publication date: November 10, 2022Inventors: Kazunori HASEGAWA, SATOSHI AWATA
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Patent number: 11444010Abstract: A semiconductor device includes: a semiconductor chip including a field effect transistor for switching; a die pad on which the semiconductor chip is mounted via a first bonding material; a lead electrically connected to a pad for source of the semiconductor chip through a metal plate; a lead coupling portion formed integrally with the lead; and a sealing portion for sealing them. A back surface electrode for drain of the semiconductor chip and the die pad are bonded via the first bonding material, the metal plate and the pad for source of the semiconductor chip are bonded via a second bonding material, and the metal plate and the lead coupling portion are bonded via a third bonding material. The first, second, and third bonding materials have conductivity, and an elastic modulus of each of the first and second bonding materials is lower than that of the third bonding material.Type: GrantFiled: October 1, 2020Date of Patent: September 13, 2022Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kazunori Hasegawa, Yuichi Yato, Hiroyuki Nakamura, Yukihiro Sato, Hiroya Shimoyama
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Patent number: 11435967Abstract: An image forming system includes a plurality of image forming apparatuses and an information processing apparatus, and the plurality of image forming apparatuses include a parent apparatus and a child apparatus(es). The parent apparatus transmits, when receiving a print instruction that is transmitted from the child apparatus for outputting operated by a user, print data to the child apparatus for outputting. The parent apparatus transmits, when transmission instruction data is included in the print data, print image data included in the print data to a transmission destination apparatus such as a child apparatus other than the child apparatus for outputting, the information processing apparatus and a further external apparatus with which the parent apparatus can perform communication via a network.Type: GrantFiled: August 25, 2021Date of Patent: September 6, 2022Assignee: SHARP KABUSHIKI KAISHAInventors: Kazunori Hasegawa, Satoshi Awata
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Publication number: 20220066709Abstract: An image forming system includes a plurality of image forming apparatuses and an information processing apparatus, and the plurality of image forming apparatuses include a parent apparatus and a child apparatus(es). The parent apparatus transmits, when receiving a print instruction that is transmitted from the child apparatus for outputting operated by a user, print data to the child apparatus for outputting. The parent apparatus transmits, when transmission instruction data is included in the print data, print image data included in the print data to a transmission destination apparatus such as a child apparatus other than the child apparatus for outputting, the information processing apparatus and a further external apparatus with which the parent apparatus can perform communication via a network.Type: ApplicationFiled: August 25, 2021Publication date: March 3, 2022Inventors: Kazunori HASEGAWA, SATOSHI AWATA
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Publication number: 20210118781Abstract: A semiconductor device includes: a semiconductor chip including a field effect transistor for switching; a die pad on which the semiconductor chip is mounted via a first bonding material; a lead electrically connected to a pad for source of the semiconductor chip through a metal plate; a lead coupling portion formed integrally with the lead; and a sealing portion for sealing them. A back surface electrode for drain of the semiconductor chip and the die pad are bonded via the first bonding material, the metal plate and the pad for source of the semiconductor chip are bonded via a second bonding material, and the metal plate and the lead coupling portion are bonded via a third bonding material. The first, second, and third bonding materials have conductivity, and an elastic modulus of each of the first and second bonding materials is lower than that of the third bonding material.Type: ApplicationFiled: October 1, 2020Publication date: April 22, 2021Inventors: Kazunori HASEGAWA, Yuichi YATO, Hiroyuki NAKAMURA, Yukihiro SATO, Hiroya SHIMOYAMA
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Patent number: 10298242Abstract: A phase control oscillator includes a voltage control oscillator, a phase comparator, a loop filter, and a storage unit. The loop filter is configured such that if the phase control oscillator starts operating, the loop filter outputs a control voltage based on phase difference information to the voltage control oscillator. The storage unit stores deviation information indicative of a deviation between a phase difference when the loop filter outputs the control voltage in the case where the phase control oscillator starts operating and the phase difference indicated by the phase difference information. After the loop filter outputs the control voltage in response to the phase control oscillator starting operating, the loop filter outputs the control voltage based on the phase difference information output from the phase comparator and the deviation information stored in the storage unit, to the voltage control oscillator.Type: GrantFiled: March 13, 2018Date of Patent: May 21, 2019Assignee: NIHON DEMPA KOGYO CO., LTD.Inventors: Ken Miyahara, Kazunori Hasegawa
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Patent number: 10262927Abstract: Reliability of a semiconductor device is improved. For this, embodied is a basic idea that a semiconductor chip (CHP1) mounted on an Ag layer (AGL) is fixed by using a temporarily fixing material (TA) having tackiness without forming the temporarily fixing material (TA) on a surface of the Ag layer (AGL) having a porous structure as much as possible, is realized. More specifically, the temporarily fixing material (TA) is supplied so as to have a portion made in contact with a chip mounting part (TAB), and the semiconductor chip (CHP1) is also mounted on the Ag layer (AGL) so that one portion of a rear surface of the semiconductor chip (CHP1) is made in contact with the temporarily fixing material (TA).Type: GrantFiled: July 23, 2015Date of Patent: April 16, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kazunori Hasegawa, Hiroi Oka
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Publication number: 20180269883Abstract: A phase control oscillator includes a voltage control oscillator, a phase comparator, a loop filter, and a storage unit. The loop filter is configured such that if the phase control oscillator starts operating, the loop filter outputs a control voltage based on phase difference information to the voltage control oscillator. The storage unit stores deviation information indicative of a deviation between a phase difference when the loop filter outputs the control voltage in the case where the phase control oscillator starts operating and the phase difference indicated by the phase difference information. After the loop filter outputs the control voltage in response to the phase control oscillator starting operating, the loop filter outputs the control voltage based on the phase difference information output from the phase comparator and the deviation information stored in the storage unit, to the voltage control oscillator.Type: ApplicationFiled: March 13, 2018Publication date: September 20, 2018Applicant: NIHON DEMPA KOGYO CO., LTD.Inventors: Ken MIYAHARA, Kazunori HASEGAWA
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Publication number: 20180247884Abstract: Reliability of a semiconductor device is improved. For this, embodied is a basic idea that a semiconductor chip (CHP1) mounted on an Ag layer (AGL) is fixed by using a temporarily fixing material (TA) having tackiness without forming the temporarily fixing material (TA) on a surface of the Ag layer (AGL) having a porous structure as much as possible, is realized. More specifically, the temporarily fixing material (TA) is supplied so as to have a portion made in contact with a chip mounting part (TAB), and the semiconductor chip (CHP1) is also mounted on the Ag layer (AGL) so that one portion of a rear surface of the semiconductor chip (CHP1) is made in contact with the temporarily fixing material (TA).Type: ApplicationFiled: July 23, 2015Publication date: August 30, 2018Inventors: Kazunori HASEGAWA, Hiroi OKA
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Patent number: 9818678Abstract: To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W1 and a narrow part (a second portion) with a second width W2. When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.Type: GrantFiled: March 23, 2014Date of Patent: November 14, 2017Assignee: Renesas Electronics CorporationInventors: Jumpei Konno, Takafumi Nishita, Nobuhiro Kinoshita, Kazunori Hasegawa, Michiaki Sugiyama
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Patent number: 9455240Abstract: Reliability of a semiconductor device is improved. Each of a plurality of terminals formed on a chip mounting surface included in a wiring substrate has a shape in which a narrow width portion is arranged between adjacent wide width portions in plan view. Moreover, a center of a tip end surface of each of a plurality of protruding electrodes formed on a semiconductor chip mounted on the wiring substrate is arranged at a position where it overlaps the narrow width portion in plan view, and the plurality of terminals and the plurality of protruding electrodes are electrically connected to each other via a solder member.Type: GrantFiled: December 23, 2013Date of Patent: September 27, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Jumpei Konno, Takafumi Nishita, Nobuhiro Kinoshita, Kazunori Hasegawa, Michiaki Sugiyama
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Publication number: 20140320110Abstract: A measuring apparatus for measuring a characteristic of a crystal unit includes an input unit, a measuring unit, a storage unit, and a calibrating unit. The input unit is configured to input a measurement signal into the crystal unit. The measuring unit is configured to measure the characteristic of the crystal unit based on an output signal output from the crystal unit with respect to the measurement signal. The storage unit is configured to associate calibration data with a measuring condition to measure the characteristic of the crystal unit, and store the associated data. The calibration data is generated based on a measurement result measured by the measuring unit with connecting a short-circuit element instead of the crystal unit. The calibrating unit is configured to calibrate the characteristic of the crystal unit measured by the measuring unit based on the calibration data.Type: ApplicationFiled: April 22, 2014Publication date: October 30, 2014Applicant: NIHON DEMPA KOGYO CO., LTD.Inventors: HIROKI MATSUI, KAZUNORI HASEGAWA
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Publication number: 20140203431Abstract: To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W1 and a narrow part (a second portion) with a second width W2. When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.Type: ApplicationFiled: March 23, 2014Publication date: July 24, 2014Applicant: Renesas Electronics CorporationInventors: Jumpei KONNO, Takafumi NISHITA, Nobuhiro KINOSHITA, Kazunori HASEGAWA, Michiaki SUGIYAMA
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Publication number: 20140183759Abstract: Reliability of a semiconductor device is improved. Each of a plurality of terminals formed on a chip mounting surface included in a wiring substrate has a shape in which a narrow width portion is arranged between adjacent wide width portions in plan view. Moreover, a center of a tip end surface of each of a plurality of protruding electrodes formed on a semiconductor chip mounted on the wiring substrate is arranged at a position where it overlaps the narrow width portion in plan view, and the plurality of terminals and the plurality of protruding electrodes are electrically connected to each other via a solder member.Type: ApplicationFiled: December 23, 2013Publication date: July 3, 2014Applicant: Renesas Electronics CorporationInventors: Jumpei Konno, Takafumi Nishita, Nobuhiro Kinoshita, Kazunori Hasegawa, Michiaki Sugiyama
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Patent number: 8701972Abstract: To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W1 and a narrow part (a second portion) with a second width W2. When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.Type: GrantFiled: August 29, 2013Date of Patent: April 22, 2014Assignee: Renesas Electronics CorporationInventors: Takafumi Nishita, Nobuhiro Kinoshita, Jumpei Konno, Michiaki Sugiyama, Kazunori Hasegawa
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Publication number: 20140004661Abstract: To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W1 and a narrow part (a second portion) with a second width W2. When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.Type: ApplicationFiled: August 29, 2013Publication date: January 2, 2014Applicant: Renesas Electronics CorporationInventors: Jumpei KONNO, Takafumi NISHITA, Nobuhiro KINOSHITA, Kazunori HASEGAWA, Michiaki SUGIYAMA
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Patent number: 8534532Abstract: To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W1 and a narrow part (a second portion) with a second width W2. When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.Type: GrantFiled: June 24, 2012Date of Patent: September 17, 2013Assignee: Renesas Electronics CorporationInventors: Jumpei Konno, Takafumi Nishita, Nobuhiro Kinoshita, Kazunori Hasegawa, Michiaki Sugiyama