Abstract: A semiconductor integrated circuit device is provided in which (i) inspection pads are arranged along one side or two opposite sides of the semiconductor integrated circuit device for bonding pads arranged along the sides other than the side or the two opposite sides and (ii) the bonding pads are connected to their respective inspection pads by connection wires The inspection is carried out by applying probe needles to the pads (inspection pads and bonding pads) arranged only along one side or two opposite sides of the semiconductor integrated circuit device. The invention also provides a semiconductor integrated circuit package with leads on four sides includes a semiconductor integrated circuit device with bonding pads laid along one pair of opposite sides of the four sides, and a table for supporting the semiconductor integrated circuit device.

Abstract: A semiconductor integrated circuit is provided whose area overhead due to provision of test points is reduced together with the test time period. In a semiconductor integrated circuit having a plurality of observation points in a tested circuit, the plurality of observation points are divided into a preset number of groups. The semiconductor integrated circuit contains at least one compressing circuit to reduce the number of bits of a multi-bit signal and to output the result (a signal of less bits) to an observable element such as an external output element or a flip-flop with a scan function. The semiconductor integrated circuit also has at least two scan chains each of which is made up with a plurality of flip-flop circuits working as shift registers. Further, the two scan chains are interconnected with a single input terminal.

Abstract: The present invention relates to an LSI which performs a self test using its built-in test function according to a test program stored in an on-chip memory. An object of the present invention is to efficiently perform the self test in the case where branching to an address out of the address space of the on-chip memory occurs. A program counter 101 stores addresses of a memory 117 and an external memory. A test program counter 108 stores an address of the memory 117. In a test mode, a program counter switching section 109 performs control so that when an address of the memory 117 is detected in the program counter 101, the address value of the program counter 101 is selected, whereas when an address of the external memory is detected in the program counter 101, the address value of the test program counter 108 is selected. A signature compression circuit 110 signature-compresses and holds the output value of the program counter 101.

Abstract: A semiconductor integrated circuit is provided whose area overhead due to provision of test points is reduced together with the test time period. In a semiconductor integrated circuit having a plurality of observation points in a tested circuit, the plurality of observation points are divided into a preset number of groups. The semiconductor integrated circuit contains at least one compressing circuit to reduce the number of bits of a multi-bit signal and to output the result (a signal of less bits) to an observable element such as an external output element or a flip-flop with a scan function. The semiconductor integrated circuit also has at least two scan chains each of which is made up with a plurality of flip-flop circuits working as shift registers. Further, the two scan chains are interconnected with a single input terminal.

Abstract: To reduce test time, test circuit configuration in which the parallel execution of a test of an I/O device and a test of an internal circuit is enabled in a semiconductor integrated circuit provided with scan test functions and a test method are provided. A test is made by a test circuit having an operational mode composed of a scan path used for observing a value of a signal fetched from an external terminal by an input buffer and setting the output value of an output buffer and a scan path used for setting a value of a signal applied to the internal circuit and observing a value of a signal output from the internal circuit in addition to a normal boundary scan operational mode. Hereby, as the test of the I/O device and the test of the internal circuit can be executed in parallel, test time can be reduced.

Abstract: The present invention relates to an LSI which performs a self test using its built-in test function according to a test program stored in an on-chip memory. An object of the present invention is to efficiently perform the self test in the case where branching to an address out of the address space of the on-chip memory occurs.

Abstract: A semiconductor integrated circuit device is provided in which (i) inspection pads are arranged along one side or two opposite sides of the semiconductor integrated circuit device for bonding pads arranged along the sides other than the side or the two opposite sides and (ii) the bonding pads are connected to their respective inspection pads by connection wires The inspection is carried out by applying probe needles to the pads (inspection pads and bonding pads) arranged only along one side or two opposite sides of the semiconductor integrated circuit device. The invention also provides a semiconductor integrated circuit package with leads on four sides includes a semiconductor integrated circuit device with bonding pads laid along one pair of opposite sides of the four sides, and a table for supporting the semiconductor integrated circuit device.

Abstract: An apparatus for providing test data used for detection of defects which occur in manufacturing functional blocks of a processor LSI is provided with a test pattern producing part for detecting a fault of the functional block at a block edge of the functional block, based on logic data of the functional block, with regard to one operation of the processor LSI which operates the functional block for the test data to be produced, the test pattern at the block edge of the functional block being such as to satisfy the conditions of an input signal to the block edge of the functional block when an instruction on the one operation is executed, and the conditions of an output signal from the block edge of the functional block being observable from the outside of the processor LSI when the instruction is executed.

Abstract: An apparatus for producing test data used for detection of defects which occur in manufacturing functional blocks of a processor LSI is provided with a test pattern producing part for detecting a fault of the functional block at a block edge of the functional block, based on logic data of the functional block, with regard to one operation of the processor LSI which operates the functional block for the test data to be produced, the test pattern at the block edge of the functional block being such as to satisfy the conditions of an input signal to the block edge of the functional block when an instruction on the one operation is executed, and the conditions of an output signal from the block edge of the functional block being observable from the outside of the processor LSI when the instruction is executed.