Patents by Inventor Kazunori HORIGUCHI

Kazunori HORIGUCHI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10388662
    Abstract: A manufacturing method of a semiconductor memory device includes disposing a first stacked body on a substrate, forming a first through via hole in the first stacked body, and determining to remove an upper portion of the first stacked body based on a comparison of a determined value of a width of the first through via hole with a reference value. The method further includes forming a second film in the first through via hole responsive to the determination to remove the upper portion of the first stacked body, removing the upper portion of the first stacked body and a portion of the second film, and disposing a second stacked body on the first stacked body and the second film. The method further includes forming a second through via hole to expose at least a portion of the second film, and removing the second film in the first through via hole.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: August 20, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kazunori Horiguchi, Takashi Ohashi
  • Publication number: 20180269223
    Abstract: A manufacturing method of a semiconductor memory device includes disposing a first stacked body on a substrate, forming a first through via hole in the first stacked body, and determining to remove an upper portion of the first stacked body based on a comparison of a determined value of a width of the first through via hole with a reference value. The method further includes forming a second film in the first through via hole responsive to the determination to remove the upper portion of the first stacked body, removing the upper portion of the first stacked body and a portion of the second film, and disposing a second stacked body on the first stacked body and the second film. The method further includes forming a second through via hole to expose at least a portion of the second film, and removing the second film in the first through via hole.
    Type: Application
    Filed: September 5, 2017
    Publication date: September 20, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Kazunori HORIGUCHI, Takashi OHASHI
  • Patent number: 9917097
    Abstract: According to an embodiment, a method of manufacturing a semiconductor device includes forming a layered body by alternately stacking a first film and a second film in a plurality of layers, and etching a portion of the layered body to penetrate the layered body from a top to a bottom to form a predetermined shape. The second film includes a first processing object film having a predetermined composition and a second processing object film having a composition that causes the second processing object film to be etched by the etching more easily than the first processing object film. The second processing object film is included as at least one of layers of the second film.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: March 13, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Kazunori Horiguchi
  • Publication number: 20170200732
    Abstract: According to an embodiment, a method of manufacturing a semiconductor device includes forming a layered body by alternately stacking a first film and a second film in a plurality of layers, and etching a portion of the layered body to penetrate the layered body from a top to a bottom to form a predetermined shape. The second film includes a first processing object film having a predetermined composition and a second processing object film having a composition that causes the second processing object film to be etched by the etching more easily than the first processing object film. The second processing object film is included as at least one of layers of the second film.
    Type: Application
    Filed: March 4, 2016
    Publication date: July 13, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Kazunori HORIGUCHI
  • Patent number: 9627218
    Abstract: According to one embodiment, a mask material is formed on a processing layer, a mask pattern with a top surface and a bottom surface is formed on the mask material, a protective film is formed on the top surface of the mask pattern, and after the formation of the protective film, the bottom surface of the mask pattern is etched in a depth direction.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: April 18, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazunori Horiguchi
  • Publication number: 20160247687
    Abstract: According to one embodiment, a mask material is formed on a processing layer, a mask pattern with a top surface and a bottom surface is formed on the mask material, a protective film is formed on the top surface of the mask pattern, and after the formation of the protective film, the bottom surface of the mask pattern is etched in a depth direction.
    Type: Application
    Filed: June 3, 2015
    Publication date: August 25, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Kazunori HORIGUCHI
  • Patent number: 9391086
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a stacked body in which a spacer film and an electrode film are alternately stacked each in a plurality of layers, and a pillar member disposed in the stacked body and penetrating the stacked body in a thickness direction. The pillar member includes an inter-electrode insulating film, a charge accumulation film, a tunnel insulating film, and a channel semiconductor film in this order from a side in contact with the stacked body. The stacked body has a taper angle of 90° in a vertical cross section of the stacked body including the pillar member.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: July 12, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Eiichi Soda, Kazunori Horiguchi
  • Publication number: 20160005603
    Abstract: In a manufacturing method of a semiconductor device according to an embodiment, a processing target film is formed above a substrate. A buffer layer in a polycrystalline state or an amorphous state is formed on the processing target film. A mask material is formed on the buffer layer. The processing target film is etched using the mask material as a mask. The buffer layer has an etching rate smaller than the processing target film.
    Type: Application
    Filed: September 8, 2014
    Publication date: January 7, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Kazunori HORIGUCHI
  • Patent number: 9218972
    Abstract: In a manufacturing method of a semiconductor device according to an embodiment, a processing target film is formed above a substrate. A buffer layer in a polycrystalline state or an amorphous state is formed on the processing target film. A mask material is formed on the buffer layer. The processing target film is etched using the mask material as a mask. The buffer layer has an etching rate smaller than the processing target film.
    Type: Grant
    Filed: September 8, 2014
    Date of Patent: December 22, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Kazunori Horiguchi
  • Patent number: 8815740
    Abstract: A method for forming a pattern according to an embodiment, includes forming above a first film film patterns of a second film; forming film patterns of the first film by etching the first film using the film patterns of the second film as a mask; converting the film patterns of the second film into film patterns whose width are narrower than the film patterns of the first film by performing a slimming process; forming film patterns of a third film on both sidewalls of the film patterns of the first film and the film patterns of the second film after the slimming process; and etching the first film using the film patterns of the third film as a mask after the film patterns of the second film being removed.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: August 26, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazunori Horiguchi, Takashi Ohashi
  • Publication number: 20140057441
    Abstract: A method for forming a pattern according to an embodiment, includes forming above a first film film patterns of a second film; forming film patterns of the first film by etching the first film using the film patterns of the second film as a mask; converting the film patterns of the second film into film patterns whose width are narrower than the film patterns of the first film by performing a slimming process; forming film patterns of a third film on both sidewalls of the film patterns of the first film and the film patterns of the second film after the slimming process; and etching the first film using the film patterns of the third film as a mask after the film patterns of the second film being removed.
    Type: Application
    Filed: December 4, 2012
    Publication date: February 27, 2014
    Inventors: Kazunori HORIGUCHI, Takashi OHASHI