Patents by Inventor Kazunori Kawamoto

Kazunori Kawamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7190027
    Abstract: A semiconductor device includes a semiconductor substrate, a low concentration region, an intermediate concentration region, the first electrode region, and the second electrode region. The device has a current-voltage characteristic having the first and second break points. The voltage of the first break point is equal to or smaller than that of the second break point. The device has a maximum current density when the device is applied with an electrostatic discharge surge. The current density of the first break point is smaller than the maximum current density, and the current density of the second break point is larger than the maximum current density.
    Type: Grant
    Filed: July 15, 2004
    Date of Patent: March 13, 2007
    Assignee: Denso Corporation
    Inventors: Shigeki Takahashi, Kazunori Kawamoto
  • Publication number: 20050029589
    Abstract: A semiconductor device includes a semiconductor substrate, a low concentration region, an intermediate concentration region, the first electrode region, and the second electrode region. The device has a current-voltage characteristic having the first and second break points. The voltage of the first break point is equal to or smaller than that of the second break point. The device has a maximum current density when the device is applied with an electrostatic discharge surge. The current density of the first break point is smaller than the maximum current density, and the current density of the second break point is larger than the maximum current density.
    Type: Application
    Filed: July 15, 2004
    Publication date: February 10, 2005
    Inventors: Shigeki Takahashi, Kazunori Kawamoto
  • Patent number: 5153700
    Abstract: Semiconductor chips are mounted in a supporting semiconductor substrate, with matching anisotropic (crystal plane) faces on the chips and substrate. The chips may extend above the substrate to facilitate connection together.
    Type: Grant
    Filed: January 22, 1991
    Date of Patent: October 6, 1992
    Assignees: Nippondenso Co., Ltd., Nippon Soken Inc.
    Inventors: Fumio Ohara, Toshiyuki Kawai, Nobuyoshi Sakakibara, Seizi Huzino, Tadashi Hattori, Kazunori Kawamoto
  • Patent number: 4989064
    Abstract: A first PSG film having a control hole is formed on a silicon substrate formed having a circuit, and a first aluminum alloy line layer resistive to stress migration made of Al-Si alloy is formed on the first PSG film, so as to electrically contact, via the contact hole, the surface of a semiconductor substrate. The alloy line layer is formed by use of a sputtering method, and the crystal face is oriented, mainly in the (111) plane, by controlling the substrate temperature at the time of sputtering, as well as the Ar gas pressure, the alloy depositing rate, and the degree of vacuum prior to the commencement of alloy depositing. The grain size l of the alloy crystal is set so as to satisfy "(W/14)<l<W" with respect to the width W of the line formed by etching, and preferably to also satisfy "(W/4)<l<(W/1.5)".
    Type: Grant
    Filed: July 5, 1989
    Date of Patent: January 29, 1991
    Assignee: Nippondenso Co., Ltd.
    Inventors: Ryoichi Kubokoya, Yasushi Higuchi, Kazunori Kawamoto