Patents by Inventor Kazunori Kitamura
Kazunori Kitamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9732183Abstract: A redundant part of a plated through hole that is formed in a printed wiring board is removed by a back drilling method; a penetration hole is filled entirely with a curable resin composition for hole filling; the curable resin composition is initially heated at a temperature less than 100° C. so that a curing rate of the curable resin composition may be 60% to 85%; and the curable resin composition is subsequently heated at a temperature 130° C. to 200° C. so that the curable resin composition may be cured completely, where the curable resin composition contains 1 part by mass to 200 parts by mass of a curing agent with respect to 100 parts by mass of liquid epoxy resin, and contains no solvent.Type: GrantFiled: August 31, 2016Date of Patent: August 15, 2017Assignee: SAN-EI KAGAKU CO., LTD.Inventors: Yukihiro Usui, Kazuya Takahashi, Kazunori Kitamura
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Publication number: 20170066868Abstract: A redundant part of a plated through hole that is formed in a printed wiring board is removed by a back drilling method; a penetration hole is filled entirely with a curable resin composition for hole filling; the curable resin composition is initially heated at a temperature less than 100° C. so that a curing rate of the curable resin composition may be 60% to 85%; and the curable resin composition is subsequently heated at a temperature 130° C. to 200° C. so that the curable resin composition may be cured completely, where the curable resin composition contains 1 part by mass to 200 parts by mass of a curing agent with respect to 100 parts by mass of liquid epoxy resin, and contains no solvent.Type: ApplicationFiled: August 31, 2016Publication date: March 9, 2017Inventors: Yukihiro USUI, Kazuya TAKAHASHI, Kazunori KITAMURA
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Patent number: 9565754Abstract: The present invention provides a solder-mounted board which realizes reliable mounting of a component thereon; a method for producing the board; and a semiconductor device. The solder-mounted board includes a substrate; a wiring layer; a solder pad for mounting a component by the mediation of the solder; and an insulating layer which covers the wiring layer such that at least the solder pad is exposed, the wiring layer, the solder pad, and the insulating layer being provided on at least one surface of the substrate, wherein the insulating layer is formed of a first insulating layer provided on the substrate and the wiring layer, and a second insulating layer provided on at least a portion of the first insulating layer.Type: GrantFiled: December 12, 2012Date of Patent: February 7, 2017Assignee: SAN-EI KAGAKU CO., LTD.Inventor: Kazunori Kitamura
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Patent number: 9415469Abstract: The present invention provides a solder bump formation resin composition which ensures resist (e.g., dry film) removability and which exhibits excellent solder bonding performance, even when the working substrate is placed at high temperature during reflowing, baking, or a similar process. The solder bump formation resin composition contains (A) at least one species selected from among an alkali-dissoluble thermoplastic resin having an acid value (mgKOH/g) of 110 or higher, an unsaturated fatty acid polymer having an acid value of 80 or higher, and an unsaturated fatty acid-aliphatic unsaturated compound copolymer having an acid value of 50 or higher; (B) a solvent; and (C) a solder powder, and contains no activating agent.Type: GrantFiled: July 25, 2014Date of Patent: August 16, 2016Assignee: SAN-EI KAGAKU CO., LTD.Inventors: Yasuhiro Takase, Kazuki Hanada, Kazunori Kitamura
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Patent number: 9072205Abstract: A surface mounting method includes applying an active resin composition to at least part of a surface of a printed wiring substrate; mounting a surface mount device on the substrate; performing reflow soldering; applying an under-filling resin into a space of interest; before and/or after applying the under-filling resin, performing a vacuum treatment and/or heating at a temperature lower than the curing reaction-initiating temperature of any of the applied active resin composition and the under-filling resin; and subsequently, thermally curing the resin composition and the under-filling resin. The active resin composition contains an epoxy resin in an amount of 100 parts by weight, a blocked carboxylic acid compound in an amount of 1-50 parts by weight and/or a carboxylic acid compound in an amount of 1-10 parts by weight, and a curing agent which can initiate curing reaction at 150° C. or higher, in an amount of 1-30 parts by weight.Type: GrantFiled: February 3, 2015Date of Patent: June 30, 2015Assignee: SAN-EI KAGAKU CO., LTD.Inventors: Kazunori Kitamura, Yasuhiro Takase, Kazuki Hanada
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Publication number: 20150158103Abstract: A surface mounting method includes applying an active resin composition to at least part of a surface of a printed wiring substrate; mounting a surface mount device on the substrate; performing reflow soldering; applying an under-filling resin into a space of interest; before and/or after applying the under-filling resin, performing a vacuum treatment and/or heating at a temperature lower than the curing reaction-initiating temperature of any of the applied active resin composition and the under-filling resin; and subsequently, thermally curing the resin composition and the under-filling resin. The active resin composition contains an epoxy resin in an amount of 100 parts by weight, a blocked carboxylic acid compound in an amount of 1-50 parts by weight and/or a carboxylic acid compound in an amount of 1-10 parts by weight, and a curing agent which can initiate curing reaction at 150° C. or higher, in an amount of 1-30 parts by weight.Type: ApplicationFiled: February 3, 2015Publication date: June 11, 2015Inventors: Kazunori KITAMURA, Yasuhiro TAKASE, Kazuki HANADA
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Publication number: 20150027768Abstract: The present invention provides a solder bump formation resin composition which ensures resist (e.g., dry film) removability and which exhibits excellent solder bonding performance, even when the working substrate is placed at high temperature during reflowing, baking, or a similar process. The solder bump formation resin composition contains (A) at least one species selected from among an alkali-dissoluble thermoplastic resin having an acid value (mgKOH/g) of 110 or higher, an unsaturated fatty acid polymer having an acid value of 80 or higher, and an unsaturated fatty acid-aliphatic unsaturated compound copolymer having an acid value of 50 or higher; (B) a solvent; and (C) a solder powder, and contains no activating agent.Type: ApplicationFiled: July 25, 2014Publication date: January 29, 2015Inventors: Yasuhiro TAKASE, Kazuki HANADA, Kazunori KITAMURA
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Patent number: 8758986Abstract: A method produces an undercoat-covered smoothed printed wiring board, requiring no step of polishing the surface of the printed wiring board. A method for producing a solder-resist-covered printed wiring board causes no depression in an area between circuit traces. A printed wiring board so produced is also described. The method for producing a printed wiring board includes applying a photo- and heat-curable resin composition onto at least a part of a surface of a printed wiring substrate; placing an optically transparent smoothing member on the resin layer; moving a hard roller on the smoothing member to thin the applied resin layer to a thickness of interest; placing a negative-image mask on the smoothing member; exposing the applied resin layer to light via the negative-image mask; removing the optically transparent smoothing member; removing a light-unexposed portion of the applied resin layer through development; and completely heat-curing the cured light-exposed portion.Type: GrantFiled: September 2, 2010Date of Patent: June 24, 2014Assignee: San-Ei Kagaku Co., Ltd.Inventors: Takeshi Saito, Kazunori Kitamura, Yukihiro Koga
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Publication number: 20130264105Abstract: The present invention provides a solder-mounted board which realizes reliable mounting of a component thereon; a method for producing the board; and a semiconductor device. The solder-mounted board includes a substrate; a wiring layer; a solder pad for mounting a component by the mediation of the solder; and an insulating layer which covers the wiring layer such that at least the solder pad is exposed, the wiring layer, the solder pad, and the insulating layer being provided on at least one surface of the substrate, wherein the insulating layer is formed of a first insulating layer provided on the substrate and the wiring layer, and a second insulating layer provided on at least a portion of the first insulating layer.Type: ApplicationFiled: December 12, 2012Publication date: October 10, 2013Applicant: SAN-EI-KAGAKU CO., LTD.Inventor: Kazunori KITAMURA
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Patent number: 8551819Abstract: Activated resinous composition contains, on the basis of epoxy resin being solid at a room temperature of 100 parts by weight, carboxylic acid compound of 1 to 10 parts by weight, hardening agent of 1 to 30 parts by weight, a hardening reaction initiation temperature of said hardening agent being 150° C. or higher, and solvent of 10 to 300 parts by weight.Type: GrantFiled: December 22, 2011Date of Patent: October 8, 2013Assignee: San-Ei Kagaku Co., Ltd.Inventors: Kazunori Kitamura, Yasuhiro Takase
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Patent number: 8232477Abstract: In a curable resin composition containing an inorganic filler, the average particle diameter of the inorganic filler is 1 ?m or less and the content of the inorganic filler is 50 wt % or less. The curable resin composition can be preferably used for a halogen-free resin substrate and the like having a small load on an environment as a hole-plugging curable resin composition as well as used to provide a hole-plugging build-up printed wiring board having a via-on-via structure (in particular, a stacked via structure) having an excellent crack-resistant property, an excellent insulation/connection reliability, and the like.Type: GrantFiled: June 30, 2009Date of Patent: July 31, 2012Assignee: San-Ei Kagaku Co., Ltd.Inventors: Kazunori Kitamura, Yukihiro Koga, Kiyoshi Sato
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Publication number: 20120168219Abstract: A surface mounting method includes applying an active resin composition to at least part of a surface of a printed wiring substrate; mounting a surface mount device on the substrate; performing reflow soldering; applying an under-filling resin into a space of interest; before and/or after applying the under-filling resin, performing a vacuum treatment and/or heating at a temperature lower than the curing reaction-initiating temperature of any of the applied active resin composition and the under-filling resin; and subsequently, thermally curing the resin composition and the under-filling resin. The active resin composition contains an epoxy resin in an amount of 100 parts by weight, a blocked carboxylic acid compound in an amount of 1-50 parts by weight and/or a carboxylic acid compound in an amount of 1-10 parts by weight, and a curing agent which can initiate curing reaction at 150° C. or higher, in an amount of 1-30 parts by weight.Type: ApplicationFiled: December 29, 2011Publication date: July 5, 2012Applicant: SAN-EI KAGAKU CO., LTDInventors: Kazunori KITAMURA, Yasuhiro TAKASE, Kazuki HANADA
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Publication number: 20120153009Abstract: Activated resinous composition contains, on the basis of epoxy resin being solid at a room temperature of 100 parts by weight, carboxylic acid compound of 1 to 10 parts by weight, hardening agent of 1 to 30 parts by weight, a hardening reaction initiation temperature of said hardening agent being 150° C. or higher, and solvent of 10 to 300 parts by weight.Type: ApplicationFiled: December 22, 2011Publication date: June 21, 2012Applicant: SAN-EI KAGAKU CO., LTD.Inventors: Kazunori KITAMURA, Yasuhiro TAKASE
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Publication number: 20110132639Abstract: A method produces an undercoat-covered smoothed printed wiring board, requiring no step of polishing the surface of the printed wiring board. A method for producing a solder-resist-covered printed wiring board causes no depression in an area between circuit traces. A printed wiring board so produced is also described. The method for producing a printed wiring board includes applying a photo- and heat-curable resin composition onto at least a part of a surface of a printed wiring substrate; placing an optically transparent smoothing member on the resin layer; moving a hard roller on the smoothing member to thin the applied resin layer to a thickness of interest; placing a negative-image mask on the smoothing member; exposing the applied resin layer to light via the negative-image mask; removing the optically transparent smoothing member; removing a light-unexposed portion of the applied resin layer through development; and completely heat-curing the cured light-exposed portion.Type: ApplicationFiled: September 2, 2010Publication date: June 9, 2011Applicant: SAN-EI KAGAKU CO., LTD.Inventors: Takeshi SAITO, Kazunori KITAMURA, Yukihiro KOGA
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Publication number: 20110031300Abstract: Activated resinous composition contains, on the basis of epoxy resin being solid at a room temperature of 100 parts by weight, carboxylic acid compound of 1 to 10 parts by weight, hardening agent of 1 to 30 parts by weight, a hardening reaction initiation temperature of said hardening agent being 150° C. or higher, and solvent of 10 to 300 parts by weight.Type: ApplicationFiled: July 29, 2010Publication date: February 10, 2011Applicant: SAN-EI KAGAKU CO., LTD.Inventors: Kazunori Kitamura, Yasuhiro Takase
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Publication number: 20100006324Abstract: In a curable resin composition containing an inorganic filler, the average particle diameter of the inorganic filler is 1 ?m or less and the content of the inorganic filler is 50 wt % or less. The curable resin composition can be preferably used for a halogen-free resin substrate and the like having a small load on an environment as a hole-plugging curable resin composition as well as used to provide a hole-plugging build-up printed wiring board having a via-on-via structure (in particular, a stacked via structure) having an excellent crack-resistant property, an excellent insulation/connection reliability, and the like.Type: ApplicationFiled: June 30, 2009Publication date: January 14, 2010Applicant: SAN-EI KAGAKU CO., LTD.Inventors: Kazunori KITAMURA, Yukihiro Koga, Kiyoshi Sato
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Patent number: 7410673Abstract: The thermosetting resin composition which is valuable for an undercoat of a printed wiring board, and does not leave an air bubble in a cured film, and makes the surface polishing easy and can form a smooth printed wiring board comprises (I) an adduct of epoxy resin with unsaturated aliphatic acid, (II) a (meth) acrylate, (III) a radical polymerization initiator, (IV) a crystallizable epoxy resin, and (V) a latent curing agent.Type: GrantFiled: August 18, 2004Date of Patent: August 12, 2008Assignee: San-ei Kagaku Co., Ltd.Inventors: Kiyoshi Sato, Kazunori Kitamura
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Patent number: 7396885Abstract: A photo-setting and thermosetting resin composition comprises (I) a partial adduct of epoxy resin with unsaturated aliphatic acid, (II) (meth)acrylates, (III) a photocrosslinking agent, (IV) liquid epoxy resin, and (V) a latent curing agent. The resin composition can be easily charged and plugged into a through-hole, does not drip down, and can be effectively photo-set and thermoset. A photo-set product prepared of the resin composition can be easily polished. A plugged-through-hole printed wiring (substrate) board prepared of the resin composition does not cause defects such as hollows, cracks, blisters, peelings and so on, is excellent in solder-resistance, does not corrode a metal part, and can produce an appliance of high reliability and long life which does not occur short circuit and poor electrical connection.Type: GrantFiled: September 12, 2002Date of Patent: July 8, 2008Assignee: SAN-EI Kagaku Co., Ltd.Inventors: Kiyoshi Sato, Kazunori Kitamura
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Publication number: 20070188093Abstract: An organic electroluminescent display panel includes a substrate, a plurality of first electrodes forming parallel stripes on the substrate, a plurality of electrical insulating partitions intersecting the first electrodes, an organic electroluminescent layer formed on the first electrodes and the partitions, a plurality of second electrodes located on the organic electroluminescent layer, and a sealing film. The second electrodes form stripes parallel with the partitions. An organic electroluminescent element is formed at each intersection of the first and second electrodes. The sealing film covers exposed portions of the first electrodes, the organic electroluminescent layer, the partitions, and the second electrodes. Each partition has an inverse tapered portion with a widened distal end.Type: ApplicationFiled: February 16, 2007Publication date: August 16, 2007Inventors: Yoshiaki Nagara, Kazunori Kitamura, Yoshifumi Fujita, Hiromu Iwata, Takeshi Yamaguchi, Yoshifumi Kato
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Publication number: 20060042832Abstract: A multilayer circuit board comprises a conductor wiring layer, and an insulation layer, wherein the conductor wiring layer and the insulation layer are laminated alternately, wherein the conductor wiring layer is electrically connected by a via through the insulation layer, wherein the via is filled with a conductor material, and wherein the conductor material is junctured to the conductor wiring layer with an alloy.Type: ApplicationFiled: August 27, 2004Publication date: March 2, 2006Inventors: Kiyoshi Sato, Kazunori Kitamura