Patents by Inventor Kazunori Kumagai
Kazunori Kumagai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10976985Abstract: A recording medium recording a program for causing a computer to execute a process including: acquiring a display target time by adding a fixed time to an average process time, which is an average of a sum of past times demanded for compression, network transfer, and decompression; acquiring a second time point when a decompression process of a data body is completed after reception of data which includes a first time point before a server compresses the data body; acquiring a current process time which indicates a sum of times demanded for compression, network transfer, and decompression of the data body by subtracting the first time point from the second time point; acquiring an adjustment time by subtracting the current process time from the display target time; displaying the data body by delaying the adjustment time; and updating a past average process time by including the current process time.Type: GrantFiled: April 21, 2020Date of Patent: April 13, 2021Assignee: FUJITSU LIMITEDInventors: Yoshiyuki Kato, Yukihiko Furumoto, Kazunori Kumagai
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Publication number: 20200341715Abstract: A recording medium recording a program for causing a computer to execute a process including: acquiring a display target time by adding a fixed time to an average process time, which is an average of a sum of past times demanded for compression, network transfer, and decompression; acquiring a second time point when a decompression process of a data body is completed after reception of data which includes a first time point before a server compresses the data body; acquiring a current process time which indicates a sum of times demanded for compression, network transfer, and decompression of the data body by subtracting the first time point from the second time point; acquiring an adjustment time by subtracting the current process time from the display target time; displaying the data body by delaying the adjustment time; and updating a past average process time by including the current process time.Type: ApplicationFiled: April 21, 2020Publication date: October 29, 2020Applicant: FUJITSU LIMITEDInventors: Yoshiyuki KATO, YUKIHIKO FURUMOTO, Kazunori Kumagai
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Patent number: 9785733Abstract: A fillet at the connection between a round land and a connecting line by calculating a first point of contact (POC) between the connecting line and a first circle and a second POC between the round land and the first circle, the first circle being in contact with the round land and the connecting line; calculating a third POC between the round land and a second circle and a fourth POC between the connecting line and the second circle, the second circle being in contact with the round land and the connecting line at the opposite side of the first circle; and calculating the arc fillet defined as a region surrounded by a first arc between the first and second POCs, a second arc between the third and fourth POCs, a third arc between the fourth and first POCs, and a line segment between the second and third POCs.Type: GrantFiled: October 21, 2015Date of Patent: October 10, 2017Assignee: FUJITSU LIMITEDInventors: Yoshitaka Nishio, Kazunori Kumagai
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Publication number: 20160378900Abstract: A non-transitory computer-readable storage medium storing a circuit design support program that causes a computer to execute a process including generating topology data indicating wiring states of components in a circuit to be designed based on circuit data, the topology data including at least one coupling line between each pair of nodes including at least one first node and at least one second node, each of the at least one first node corresponding to each of the components and each of the at least one second node corresponding to each of at least one branch point in a wiring of the circuit when the wiring includes the at least one branch point, and displaying the generated topology data and an input field for receiving an input of restrictive data indicating restrictive requirements for each of the at least one coupling line between each of the nodes.Type: ApplicationFiled: June 20, 2016Publication date: December 29, 2016Applicant: FUJITSU LIMITEDInventors: Ryoko OKUBO, Mitsuru Sato, Kazunori Kumagai
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Publication number: 20160154919Abstract: A fillet at the connection between a round land and a connecting line by calculating a first point of contact (POC) between the connecting line and a first circle and a second POC between the round land and the first circle, the first circle being in contact with the round land and the connecting line; calculating a third POC between the round land and a second circle and a fourth POC between the connecting line and the second circle, the second circle being in contact with the round land and the connecting line at the opposite side of the first circle; and calculating the arc fillet defined as a region surrounded by a first arc between the first and second POCs, a second arc between the third and fourth POCs, a third arc between the fourth and first POCs, and a line segment between the second and third POCs.Type: ApplicationFiled: October 21, 2015Publication date: June 2, 2016Applicant: FUJITSU LIMITEDInventors: Yoshitaka Nishio, Kazunori Kumagai
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Patent number: 8898615Abstract: A receiving unit receives specification of two parts to be connected by wirings and the number of wirings connecting the two parts. A generating unit generates a schematic route connecting the two parts on a substrate with a width in accordance with the number of wirings received by the receiving unit. A derivation unit derives the number of arrangeable wirings by checking interference whether the schematic route generated by the generating unit is capable of being arranged on the substrate.Type: GrantFiled: November 14, 2013Date of Patent: November 25, 2014Assignee: Fujitsu LimitedInventors: Kazunori Kumagai, Takahiko Orita
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Patent number: 8856717Abstract: A circuit board design aid is achieved by generating a shield pattern for a wiring pattern including a pattern element in a circuit board by increasing a width of a geometry of the pattern element by an amount corresponding to a shield pattern spacing set as a preset pattern generation condition. A prohibition region is generated based on a geometry of an element for which a clearance check is to be performed located around the wiring pattern and a clearance condition between the element for performing a clearance check and the wiring pattern. Then, the shield pattern is generated by excluding the geometry of the prohibition region from the geometry of the basic shield pattern element.Type: GrantFiled: September 16, 2010Date of Patent: October 7, 2014Assignee: Fujitsu LimitedInventors: Kazunori Kumagai, Eiichi Konno
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Patent number: 8793643Abstract: A wiring-design support device supports wiring design of a printed circuit board. The processor executes a process that includes holding, in the memory, wiring information including information relating to a plurality of signal wires to be wired in parallel between two components on the printed circuit board, generating a wiring route illustrating a wiring area where the plurality of signal wires are wired between the two components and displaying the wiring route on a display unit based on the wiring information held in the holding. And the processor generates, upon or after the wiring route generated, a detailed wiring where each of the plurality of signal wires is wired along the wiring route based on the wiring route and a wiring rule included in the wiring information, and displaying the detailed wiring on the display unit along with the wiring route.Type: GrantFiled: September 24, 2012Date of Patent: July 29, 2014Assignee: Fujitsu LimitedInventors: Yoshitaka Nishio, Kazunori Kumagai
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Publication number: 20140201696Abstract: A receiving unit receives specification of two parts to be connected by wirings and the number of wirings connecting the two parts. A generating unit generates a schematic route connecting the two parts on a substrate with a width in accordance with the number of wirings received by the receiving unit. A derivation unit derives the number of arrangeable wirings by checking interference whether the schematic route generated by the generating unit is capable of being arranged on the substrate.Type: ApplicationFiled: November 14, 2013Publication date: July 17, 2014Applicant: FUJITSU LIMITEDInventors: Kazunori KUMAGAI, Takahiko ORITA
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Patent number: 8484600Abstract: A computer-readable medium storing a design program causing a computer to execute a process is provided. The process includes virtually routing, when routing of a wire to be connected between a first component and a second component at least one of which includes a swapping pin is being designed, the wire to be connected between a first pin of the first component and a first counterpart pin of the second component such that implementation of an actual routed wire connected therebetween is secured regardless of a net allocated to the swapping pin, and swapping one of the virtually routed first pin and the virtually routed first counterpart pin with the swapping pin such that the net allocated to the swapping pin is identical to a net allocated to the other one of the virtually routed first pin and the virtually routed first counterpart pin.Type: GrantFiled: August 30, 2011Date of Patent: July 9, 2013Assignee: Fujitsu LimitedInventors: Yoshitaka Nishio, Eiichi Konno, Kazunori Kumagai, Motoyuki Tanisho, Toshiyasu Sakata
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Patent number: 8443333Abstract: A non-transitory computer-readable recording medium storing a design supporting program causes a computer to perform: acquiring non-complying line lengths of a plurality of wiring paths; drawing for each of the wiring paths a wiring pattern connecting a transmission origin and a transmission destination based on a line length and a wiring route of the wiring path; and controlling the drawing to draw a line for each of the wiring paths, the line being divided into a first line amounting to a non-complying line length acquired at the acquiring and a second line being a wiring pass less the non-complying line length.Type: GrantFiled: March 9, 2011Date of Patent: May 14, 2013Assignee: Fujitsu LimitedInventors: Takahiko Orita, Kazunori Kumagai, Yoshitaka Nishio, Ikuo Ohtsuka, Motoyuki Tanisho
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Patent number: 8423948Abstract: A device includes a definition unit which defines a directional graph having a grid point as a node and a line connecting adjacent grid points as a branch, a generation unit which sets a branch connecting a grid pointing a wiring prohibited area in the branches of the directional graph to the capacity of “0”, and which sets another branch to the capacity of “1”, and which connects the starting point or the end point to each grid point of the wiring terminal indicated by wiring information, thereby generating a flow network, a search unit which searches the flow network for a path of a flow having the maximum amount of flow from the starting point to the end point, and a determination unit which determines a wiring path connecting the grid point indicated by the wiring information according to the search result of the path.Type: GrantFiled: March 13, 2012Date of Patent: April 16, 2013Assignee: Fujitsu LimitedInventors: Kazunori Kumagai, Toshiyasu Sakata, Eiichi Konno
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Patent number: 8402414Abstract: A computer-readable, non-transitory medium stores therein a design support program that causes a computer executing tentative wiring processing between a first terminal group and a second terminal group in a tentative wiring area to execute a process. The process includes detecting unwired nets occurring in the tentative wiring area consequent to the tentative wiring processing; updating the tentative wiring area by expanding the tentative wiring area according to the number of unwired nets, if any unwired nets are detected at the detecting; controlling to execute the tentative wiring processing and the subsequent detecting with respect to the tentative wiring area updated at the updating; and determining the tentative wiring area to be a wiring area if no unwired nets are detected at the detecting.Type: GrantFiled: February 24, 2011Date of Patent: March 19, 2013Assignee: Fujitsu LimitedInventors: Motoyuki Tanisho, Toshiyasu Sakata, Yoshitaka Nishio, Ikuo Ohtsuka, Kazunori Kumagai
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Patent number: 8402422Abstract: A wiring design device to conduct wiring design on a printed wiring board that includes a plurality of conductive layers, the wiring design device including: noise contaminating part extracting means for extracting a part in a condition where noise contaminates a signal, the part being on a wiring-designed line, based on a route of the line and a physical condition around the route; route modification processing means for modifying the route of the line by moving the extracted part on the line in the condition where noise contaminates the signal to a position that avoids the condition where noise contaminates the signal; and line length adjusting means for conducting a line length adjustment on the line to compensate for a variation of the line length of the line when the variation of the line length of the line occurs due to modifying the route of the line.Type: GrantFiled: March 15, 2011Date of Patent: March 19, 2013Assignee: Fujitsu LimitedInventors: Toshiyasu Sakata, Eiichi Konno, Takahiko Orita, Kazunori Kumagai
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Patent number: 8286124Abstract: A printed circuit board design assisting method, device and storage medium are provided. The assisting method includes referring to the position of terminals of a grid array package part, and attributes indicating whether each of the terminals is a power source terminal or a ground terminal, and selecting the power source terminals as a terminal to be researched, searching for a new connection path between the terminal which has been selected, and one of the ground terminals, by way of a first decoupling capacitor, determining whether there is duplication of paths between the new connection path and an connection path between the terminals connected by way of a second decoupling capacitor, changing the position of the second decoupling capacitor if duplication is detected, and re-searching a connection path between the terminals by way of the second decoupling capacitor, which is not in duplicate with the new connection path.Type: GrantFiled: June 21, 2010Date of Patent: October 9, 2012Assignee: Fujitsu LimitedInventors: Toshiyasu Sakata, Eiichi Konno, Takahiko Orita, Yoshitaka Nishio, Kazunori Kumagai
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Publication number: 20120240094Abstract: A device includes a definition unit which defines a directional graph having a grid point as a node and a line connecting adjacent grid points as a branch, a generation unit which sets a branch connecting a grid pointing a wiring prohibited area in the branches of the directional graph to the capacity of “0”, and which sets another branch to the capacity of “1”, and which connects the starting point or the end point to each grid point of the wiring terminal indicated by wiring information, thereby generating a flow network, a search unit which searches the flow network for a path of a flow having the maximum amount of flow from the starting point to the end point, and a determination unit which determines a wiring path connecting the grid point indicated by the wiring information according to the search result of the path.Type: ApplicationFiled: March 13, 2012Publication date: September 20, 2012Applicant: FUJITSU LIMITEDInventors: Kazunori KUMAGAI, Toshiyasu Sakata, Eiichi Konno
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Publication number: 20120117529Abstract: A computer-readable medium storing a design program causing a computer to execute a process is provided. The process includes virtually routing, when routing of a wire to be connected between a first component and a second component at least one of which includes a swapping pin is being designed, the wire to be connected between a first pin of the first component and a first counterpart pin of the second component such that implementation of an actual routed wire connected therebetween is secured regardless of a net allocated to the swapping pin, and swapping one of the virtually routed first pin and the virtually routed first counterpart pin with the swapping pin such that the net allocated to the swapping pin is identical to a net allocated to the other one of the virtually routed first pin and the virtually routed first counterpart pin.Type: ApplicationFiled: August 30, 2011Publication date: May 10, 2012Applicant: FUJITSU LIMITEDInventors: Yoshitaka Nishio, Eiichi Konno, Kazunori Kumagai, Motoyuki Tanisho, Toshiyasu Sakata
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Publication number: 20110231810Abstract: A computer-readable, non-transitory medium stores therein a design support program that causes a computer executing tentative wiring processing between a first terminal group and a second terminal group in a tentative wiring area to execute a process. The process includes detecting unwired nets occurring in the tentative wiring area consequent to the tentative wiring processing; updating the tentative wiring area by expanding the tentative wiring area according to the number of unwired nets, if any unwired nets are detected at the detecting; controlling to execute the tentative wiring processing and the subsequent detecting with respect to the tentative wiring area updated at the updating; and determining the tentative wiring area to be a wiring area if no unwired nets are detected at the detecting.Type: ApplicationFiled: February 24, 2011Publication date: September 22, 2011Applicant: FUJITSU LIMITEDInventors: Motoyuki TANISHO, Toshiyasu SAKATA, Yoshitaka NISHIO, Ikuo OHTSUKA, Kazunori KUMAGAI
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Publication number: 20110231809Abstract: A wiring design device to conduct wiring design on a printed wiring board that includes a plurality of conductive layers, the wiring design device including: noise contaminating part extracting means for extracting a part in a condition where noise contaminates a signal, the part being on a wiring-designed line, based on a route of the line and a physical condition around the route; route modification processing means for modifying the route of the line by moving the extracted part on the line in the condition where noise contaminates the signal to a position that avoids the condition where noise contaminates the signal; and line length adjusting means for conducting a line length adjustment on the line to compensate for a variation of the line length of the line when the variation of the line length of the line occurs due to modifying the route of the line.Type: ApplicationFiled: March 15, 2011Publication date: September 22, 2011Applicant: FUJITSU LIMITEDInventors: Toshiyasu Sakata, Eiichi Konno, Takahiko Orita, Kazunori Kumagai
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Publication number: 20110225561Abstract: A non-transitory computer-readable recording medium storing a design supporting program causes a computer to perform: acquiring non-complying line lengths of a plurality of wiring paths; drawing for each of the wiring paths a wiring pattern connecting a transmission origin and a transmission destination based on a line length and a wiring route of the wiring path; and controlling the drawing to draw a line for each of the wiring paths, the line being divided into a first line amounting to a non-complying line length acquired at the acquiring and a second line being a wiring pass less the non-complying line length.Type: ApplicationFiled: March 9, 2011Publication date: September 15, 2011Applicant: FUJITSU LIMITEDInventors: Takahiko ORITA, Kazunori KUMAGAI, Yoshitaka NISHIO, Ikuo OHTSUKA, Motoyuki TANISHO