Abstract: In charging a gate of a NMOS transistor Q1, the charging speed is adjustable by varying a resistor R1. When an inputted pulse signal VIN reverses to a negative voltage, a diode D2 turns off. Then, current flows along a discharging loop formed by the gate capacitor, the resistor R1, the emitter of the transistor Q2, the base of the transistor Q2, the resistor R2 and the capacitor C1, the transformer T1 and the source of the NMOS transistor Q1. A reverse bias voltage is applied to the gate of the NMOS transistor Q1, thereby keeping the NMOS transistor Q1off-state stably.

Abstract: In charging a gate of a NMOS transistor Q1, the charging speed is adjustable by varying a resistor R1. When an inputted pulse signal VIN reverses to a negative voltage, a diode D2 turns off. Then, current flows along a discharging loop formed by the gate capacitor, the resistor R1, the emitter of the transistor Q2, the base of the transistor Q2, the resistor R2 and the capacitor C1, the transformer T1 and the source of the NMOS transistor Q1. A reverse bias voltage is applied to the gate of the NMOS transistor Q1, thereby keeping the NMOS transistor Q1 off-state stably.

Abstract: A switching power supply apparatus has a plurality of switching power supply circuits. A control IC (IC1) in a switching power supply circuit generates a PWM drive signal and a synchronizing signal, and also generates DC voltage according to a duty ratio of the PWM drive signal. A control IC (IC2) in the other switching power supply circuit is provided with the synchronizing signal from the IC1 via a transformer, and controls based on a PWM drive signal synchronized with the synchronizing signal. Therefore, switching timing completely matches among the plurality of switching power supply circuits.