Abstract: A bone nail for stabilizing a fracture. The bone nail having a head portion and a stem portion. The stem portion offset from the longitudinal axis of the head portion. The nail including a continuous passageway extending from a rear edge of the nail to a front edge of the nail. The continuous passageway including a bore extending longitudinally through the head portion and both a groove and a bore in the stem portion.

Abstract: A bone nail for stabilizing a fracture. The bone nail having a head portion and a stem portion. The stem portion offset from the longitudinal axis of the head portion. The nail including a continuous passageway extending from a rear edge of the nail to a front edge of the nail. The continuous passageway including a bore extending longitudinally through the head portion and both a groove and a bore in the stem portion.

Abstract: A bone nail for stabilizing a fracture. The bone nail having a head portion and a stem portion. The stem portion offset from the longitudinal axis of the head portion. The nail including a continuous passageway extending from a rear edge of the nail to a front edge of the nail. The continuous passageway including a bore extending longitudinally through the head portion and both a groove and a bore in the stem portion.

Abstract: A DDS achieved in size and cost reductions by removing a ROM for storing a table and the like and suppressing an operation amount is provided. A DDS includes an NCO, a DAC, and a BPF. The NCO outputs a sawtooth wave. The DAC converts either one of the sawtooth wave outputted from the NCO and a triangle wave signal converted by a waveform converting circuit based on the sawtooth wave, from a digital signal into an analog signal. The BPF receives the signal converted into the analog signal by the DAC and extracts a sine wave at a predetermined frequency from the inputted signal, by allowing a signal at a frequency within a fixed range to pass therethrough.

Abstract: Provided is a timing signal supply device that can frequently perform a phase comparison on a side of receiving a supply of a timing signal and flexibly achieve various operation modes. A GPS receiver 11 includes a baseband processing module 16 and a PN code output terminal 26. The baseband processing module 16 performs a positioning calculation based on positioning signals received from GPS satellites. The PN code output terminal 26 is configured so as to be able to output, based on the result of the positioning calculation by the baseband processing module 16, a PN code that is repeated every second in synchronization with the coordinated universal time.

Abstract: A DDS achieved in size and cost reductions by removing a ROM for storing a table and the like and suppressing an operation amount is provided. A DDS includes an NCO, a DAC, and a BPF. The NCO outputs a sawtooth wave. The DAC converts either one of the sawtooth wave outputted from the NCO and a triangle wave signal converted by a waveform converting circuit based on the sawtooth wave, from a digital signal into an analog signal. The BPF receives the signal converted into the analog signal by the DAC and extracts a sine wave at a predetermined frequency from the inputted signal, by allowing a signal at a frequency within a fixed range to pass therethrough.

Abstract: This disclosure provides a phase measuring device that can measure phase differences with high precision using the digital circuits. A phase measuring device includes a buffer delay measuring circuit and a phase difference measuring circuit which use a TDC, respectively, and a phase difference calculator. The buffer delay measuring circuit generates delay measurement data indicating a delay amount ?B between the buffers of the TDCs based on a highly precise clock signal and a sampling reference signal. The phase difference measuring circuit generates a number data row indicating a phase difference between measuring signals SS(A) and SS(B), and first and second phase difference measuring data Ds(A) and Ds(B), using the clock signal.

Abstract: The disclosed is a reference frequency generating device (11), which includes a GPS receiver (21), a PLL circuit (31), a detector (28), a memory unit (29), and a controller (22). The PLL circuit (31) controls the digitally controlled oscillator (26) based on a synchronizing control signal acquired based on a reference signal from the GPS receiver (21). The memory unit (29) stores a correspondence relation between a control value of the synchronizing control signal, and a voltage value and a temperature at that time. When the reference signal is not acquired, the controller 22 determines a holdover control signal based on the correspondence relation, and the voltage and temperature detected by the detector 28, and controls the digitally controlled oscillator (26).

Abstract: The disclosed is a reference frequency generating device (11), which includes a GPS receiver (21), a PLL circuit (31), a detector (28), a memory unit (29), and a controller (22). The PLL circuit (31) controls the digitally controlled oscillator (26) based on a synchronizing control signal acquired based on a reference signal from the GPS receiver (21). The memory unit (29) stores a correspondence relation between a control value of the synchronizing control signal, and a voltage value and a temperature at that time. When the reference signal is not acquired, the controller 22 determines a holdover control signal based on the correspondence relation, and the voltage and temperature detected by the detector 28, and controls the digitally controlled oscillator (26).

Abstract: Provided is a timing signal supply device that can frequently perform a phase comparison on a side of receiving a supply of a timing signal and flexibly achieve various operation modes. A GPS receiver 11 includes a baseband processing module 16 and a PN code output terminal 26. The baseband processing module 16 performs a positioning calculation based on positioning signals received from GPS satellites. The PN code output terminal 26 is configured so as to be able to output, based on the result of the positioning calculation by the baseband processing module 16, a PN code that is repeated every second in synchronization with the coordinated universal time.

Abstract: This disclosure provides a phase measuring device that can measure phase differences with high precision using the digital circuits. A phase measuring device includes a buffer delay measuring circuit and a phase difference measuring circuit which use a TDC, respectively, and a phase difference calculator. The buffer delay measuring circuit generates delay measurement data indicating a delay amount ?B between the buffers of the TDCs based on a highly precise clock signal and a sampling reference signal. The phase difference measuring circuit generates a number data row indicating a phase difference between measuring signals SS(A) and SS(B), and first and second phase difference measuring data Ds(A) and Ds(B), using the clock signal.

Abstract: The present invention reduces the delay time to extremely short by monitoring the output/distribution unit of the exchange node to specify the unused time slot as write destination of the data and performing priority control by the priority control signal contained in the data. The traffic congestion is resolved by performing write output to the specified time slot regardless of the communication speed of the transmission path of the data. Furthermore, the present invention aims to provide the exchange node and the exchange node control method that ensures communication quality by using the connection type as the communication method since the delay time in communication can be reduced. The exchange node 100 according to the present invention includes an input buffer unit 2, an identification unit 7, a distribution unit 5, a multiplexing circuit 9, a time slot allocation circuit 12, and an output/distribution unit 10.

Abstract: The present invention reduces the delay time to extremely short by monitoring the output/distribution unit of the exchange node to specify the unused time slot as write destination of the data and performing priority control by the priority control signal contained in the data. The traffic congestion is resolved by performing write output to the specified time slot regardless of the communication speed of the transmission path of the data. Furthermore, the present invention aims to provide the exchange node and the exchange node control method that ensures communication quality by using the connection type as the communication method since the delay time in communication can be reduced. The exchange node 100 according to the present invention includes an input buffer unit 2, an identification unit 7, a distribution unit 5, a multiplexing circuit 9, a time slot allocation circuit 12, and an output/distribution unit 10.

Abstract: The invention relates to a multi-channel type GPS receiver which is able to shorten the search time for a cold start, wherein a carrier tracking circuit 10, code tracking circuit 12, C/A code generator 14 are provided at the L1-C/A code receiving channel side, a C/A code generator 20 is provided at the L1-P code receiving channel side in addition to the code tracking circuit 16 and P code generator 18. Thereby, the code generator 20 and tracking circuit 16 are changed over and connected to each other by a switching means 22 when carrying out a search mode for a cold start. A C/A code generator 30 is provided at the L2-P code receiving channel side in addition to a carrier tracking circuit 24, code tracking circuit 26 and P code generator 28, whereby the code generator 30 is changed and connected to the tracking circuit 26 by a switching means 32 when carrying out the search mode during a cold start.

Abstract: A decimation filter includes a first circuit block for respectively delaying by one clock an input signal synchronized with a clock signal and for producing a plurality of delayed signals, adders for adding or merging by confluence buffers the delayed signals to obtain total signals and for feeding the total signals to one signal line, and a second circuit block for counting pulses of the total signals. The filter provides an analog-to-digital converter which processes signals at a high speed and which is resistive against overflow.

Abstract: A rapid single-flux-quantum RSFQ logic circuit includes a first circuit portion having a first end grounded and having in-series connected first and second Josephson junctions. A second circuit portion has a first end grounded and has in-series connected third and fourth Josephson junctions. A first inductance element connects a second end of the first circuit portion to a second end of the second circuit portion. A tap is provided in the first inductance element, an input current signal being supplied to the tap. A bias current source is connected to a first connection node between the first and second Josephson junctions. A second inductance element connects the first connection node to a second connection node between the third and fourth Josephson junctions. A superconducting quantum interference device has fifth and sixth Josephson junctions and is coupled to the second inductance element through a magnetic field.

Abstract: A rapid single-flux-quantum RSFQ logic circuit includes a first circuit portion having a first end grounded and having in-series connected first and second Josephson junctions. A second circuit portion has a first end grounded and has in-series connected third and fourth Josephson junctions. A first inductance element connects a second end of the first circuit portion to a second end of the second circuit portion. A tap is provided in the first inductance element, an input current signal being supplied to the tap. A bias current source is connected to a first connection node between the first and second Josephson junctions. A second inductance element connects the first connection node to a second connection node between the third and fourth Josephson junctions. A superconducting quantum interference device has fifth and sixth Josephson junctions and is coupled to the second inductance element through a magnetic field.

Abstract: A superconducting circuit device of a voltage-type logic device is large in current driving capability and, accordingly, electric power consumption; however, the switching speed is not so fast, and a superconducting circuit device of a fluxoid-type logic device is small in current driving capability and, accordingly, the electric power consumption; however the switching speed is faster than that of the superconducting circuit device of the voltage-type logic device, wherein the superconducting circuit device of the voltage-type logic device and the superconducting circuit device of the fluxoid-type logic device are selectively used in a superconducting circuit such as a superconducting random access memory, a superconducting NOR circuit and a superconducting signal converting circuit so as to realize small electric power consumption and high-speed switching action.

Abstract: In the random access memory utilizing an oxide high-temperature superconductor, a first high-temperature superconductor layer 1, a non-superconductor layer 2, a second high-temperature superconductor layer 3 and a non-superconductor layer 4 are formed on an insulated substrate. The first high-temperature superconductor layer 1 is formed in a first loop, forming a memory storage superconductor quantum interference device by two Josephson junctions and a control current line I.sub.WX (6) and a bias current line I.sub.WY (8) in order to store the flux quantum. The second high-temperature superconductor layer 3 is formed in a second loop, forming a reading superconducting quantum interference device by two Josephson junctions and a control current line I.sub.RX (5) and a bias current line I.sub.RY (7).

Abstract: A reflecting mirror-equipped GPS receiving antenna apparatus comprises a reflecting mirror and a microstrip type of antenna for receiving radio waves transmitted from GPS satellites. The reflecting mirror is supported by a base member so as to be swingable about a horizontal axis as well as rotatable about a first vertical axis. The antenna is supported above the reflecting mirror so as to be rotatable about a second vertical axis which is coaxial with the first vertical axis.