Abstract: A semiconductor integrated circuit device and an inspection method for a semiconductor integrated circuit device capable of improving burn-in screening quality by improvement in an activation rate of a DSP without operating a diagnostic circuit at the time of wafer level burn-in in a semiconductor integrated circuit device incorporating an analog circuit and the diagnostic circuit for the analog circuit are provided.

Abstract: A semiconductor integrated circuit device and an inspection method for a semiconductor integrated circuit device capable of improving burn-in screening quality by improvement in an activation rate of a DSP without operating a diagnostic circuit at the time of wafer level burn-in in a semiconductor integrated circuit device incorporating an analog circuit and the diagnostic circuit for the analog circuit are provided.

Abstract: A system and method for determining measurement results of a dark-field inspection apparatus up to a microscopic area. A dark-field inspection apparatus is calibrated using a reference wafer having microroughness of an irregular asperity pattern accurately formed on a surface, and the microroughness of the surface having an ensured microroughness degree. This microroughness is measured by using an AFM, and an expected haze value is obtained based on the measured value. Then, haze of the surface of the reference wafer is measured by the dark-field inspection apparatus to be inspected to obtain an actually-measured haze value, and a difference between the expected haze value and the actually-measured haze value is obtained. Based on this difference, a haze measurement parameter of the dark-field inspection apparatus is adjusted so that the actually-measured haze value and the expected haze value match each other.

Abstract: A defect is efficiently and effectively classified by accurately determining the state of overlap between a design layout pattern and the defect. This leads to simple identification of a systematic defect. A defective image obtained through defect inspection or review of a semiconductor device is automatically pattern-matched with design layout data. A defect is superimposed on a design layout pattern for at least one layer of a target layer, a layer immediately above the target layer, and a layer immediately below the target layer. The state of overlap of the defect is determined as within the pattern, over the pattern, or outside the pattern, and the defect is automatically classified.

Abstract: A defect is efficiently and effectively classified by accurately determining the state of overlap between a design layout pattern and the defect. This leads to simple identification of a systematic defect. A defective image obtained through defect inspection or review of a semiconductor device is automatically pattern-matched with design layout data. A defect is superimposed on a design layout pattern for at least one layer of a target layer, a layer immediately above the target layer, and a layer immediately below the target layer. The state of overlap of the defect is determined as within the pattern, over the pattern, or outside the pattern, and the defect is automatically classified.

Abstract: A technology capable of ensuring measurement results of a dark-field inspection apparatus up to a microscopic area is provided. A dark-field inspection apparatus is calibrated using a bulk wafer as a reference wafer, the bulk wafer having microroughness of an irregular asperity pattern accurately formed on a surface, and the microroughness of the surface having an ensured microroughness degree. The microroughness can be more accurately formed by a chemical treatment with a chemical solution. This microroughness is measured by using an AFM, and an expected haze value is obtained based on the measured value. Then, haze of the surface of the reference wafer is measured by the dark-field inspection apparatus to be inspected to obtain an actually-measured haze value, and a difference between the expected haze value and the actually-measured haze value is obtained.

Abstract: The present invention provides a technology for suppressing occurrence of abnormality on a surface of a silicon film other than a single crystal film formed on a wafer. A silicon film is formed on a wafer in step S1 and an oxide film functioning as an abnormality suppression film for suppressing the surface abnormality is formed on the silicon surface on the wafer formed in step S10. The abnormality suppression film is formed by the surface oxidation of the polycrystalline silicon using chemical solution such as ozone water or hydrogen peroxide solution. After forming the abnormality suppression film on the silicon surface, the abnormality suppression film, for example, an abnormal growth suppression film is removed according to need, and then the process of patterning the silicon film and forming an insulating oxide film is performed.

Abstract: A manufacturing method of semiconductor device capable of suppressing or preventing formation of a dissolution region of composition atoms such as a pit in a semiconductor wafer. After oxide film on a semiconductor wafer is removed by dipping plural pieces of the semiconductor wafer accommodated in a carrier into chemical liquid containing fluoro acid, chemical liquid adhering to the semiconductor wafer is washed out of the semiconductor wafer by rinse processing using de-ionized water. At least in the rinse processing of this wet processing, light is projected to the semiconductor wafer from a light source provided on a wet etching apparatus. Adjusting electromotive force caused by battery reaction at a pn junction of the semiconductor wafer by adjusting the state of the light L enables generation of a pit in the semiconductor wafer.

Abstract: A silicon oxide film is formed on the back side of a semiconductor substrate by using a CVD apparatus of a single wafer processing type, with a silicon oxide film deposited on the upper part of trenches on the semiconductor substrate placed downward, to form element isolation comprising the silicon oxide film, and then a MISFET is formed. As a result, even in a manufacturing process using mainly the single wafer processing, in which a film is not formed or hardly formed on the back side of the semiconductor substrate, deterioration of a gate insulating film due to charging-up of the semiconductor substrate, which occurs at the time of plasma processing, for example, at the time of forming a gate electrode or ashing of a resist film, can be prevented, and contamination of the back side of the semiconductor substrate can be prevented. Further, by performing lift-off cleaning which slightly etches the silicon oxide film, the cleaning efficiency can be improved.

Abstract: An inspection system comprises an inspection machine for inspecting a work which is processed in one of the manufacturing processes of a manufacturing line and an analysis system for outputting an inspection history list obtained by making calculations from the inspected result. The inspection history list shows a matrix of first information as the inspection processes in which the work is inspected or the manufacturing processes corresponding to the inspection processes in which the work is inspected and second information as to the works inspected by the inspection machine.

Abstract: An analysis method includes one or more inspection steps for inspecting defects on a wafer, including an electrical inspection an step for inspecting electrical function of dies of the wafer, a determination step for determining whether each die is a good die or a bad die by using results obtained in the electrical inspection step, a calculation step for calculating the yield of dies without defects by using results obtained in the determination step, and an output step for outputting a result of the calculation step.