Abstract: A multilayer ceramic capacitor 1 having internal electrode layers 3, internal dielectric layers 2 having the thickness of less than 2 ?m, and external dielectric layers 20 wherein; the internal dielectric layers 2 and the external dielectric layers 20 include a plural number of dielectric particles 2a, 20a, and when y1 is ratio(D50a/D50b) of D50a and D50b where D50a is an average particle size of dielectric particles 2a included in the internal dielectric layers 2 and D50b is an average particle size of dielectric particles 20a included in the external dielectric layer 20 and located at least 5 ?m away from an internal electrode layer 3a, arranged outermost part of all the internal electrode layers, to the stacked direction, and x is thickness of the internal dielectric layer 2, y1 and x satisfy the following equations, y1??0.75x+2.275 and y1??0.75x+1.675.

Abstract: A multilayer ceramic capacitor including an internal electrode layer, an internal dielectric layer having a thickness of less than 2 ?m, and an external dielectric layer is provided, wherein the internal dielectric layer and external dielectric layer contain a plurality of dielectric particles, and when assuming that an average particle diameter of the entire dielectric particles in the internal dielectric layer is D50a (unit: ?m), an average particle diameter of the entire dielectric particles existing at a position being away at least by 5 ?m from the outermost internal electrode layer in the thickness direction is D50b (unit: ?m), a ratio (D50a/D50b) of the D50a and D50b is y (no unit), standard deviation of a particle size distribution of the entire dielectric particles in the internal dielectric layer is ? (no unit), and a ratio that dielectric particles (coarse particles) having an average particle diameter of 2.

Abstract: A multilayer ceramic capacitor comprising an internal electrode layer and a dielectric layer having a thickness of less than 2 ?m is provided, wherein the dielectric layer contains a plurality of dielectric particles, and when it is assumed that standard deviation of a particle distribution of the entire dielectric particles in the dielectric layer is ? (no unit), an average particle diameter of the entire dielectric particles in the dielectric layer is D50 (unit: ?m), and a rate that dielectric particles (coarse particles) having an average particle diameter of 2.25 times of the D50 exist in the entire dielectric particles is p (unit: %), the ? and p satisfy ?<0.130 and p<12%; by which a TC bias characteristic can be expected to be improved while maintaining various electric characteristics, particularly a sufficient permittivity, even when the interlayer dielectric layer is made thin.

Abstract: A multilayer ceramic capacitor comprising an internal electrode layer, an internal dielectric layer having a thickness of less than 2 ?m, and an external dielectric layer is provided, wherein the internal dielectric layer and external dielectric layer contain a plurality of dielectric particles, and when assuming that an average particle diameter of the entire dielectric particles in the internal dielectric layer is D50a (unit: ?m), an average particle diameter of the entire dielectric particles existing at a position being away at least by 5 ?m from the outermost internal electrode layer in the thickness direction is D50b (unit: ?m), a ratio (D50a/D50b) of the D50a and D50b is y (no unit), standard deviation of a particle size distribution of the entire dielectric particles in the internal dielectric layer is ? (no unit), and a ratio that dielectric particles (coarse particles) having an average particle diameter of 2.

Abstract: A multilayer ceramic capacitor 1 having internal electrode layers 3, internal dielectric layers 2 having the thickness of less than 2 ?m, and external dielectric layers 20 wherein; the internal dielectric layers 2 and the external dielectric layers 20 include a plural number of dielectric particles 2a, 20a, and when y1 is ratio(D50a/D50b) of D50a and D50b where D50a is an average particle size of dielectric particles 2a included in the internal dielectric layers 2 and D50b is an average particle size of dielectric particles 20a included in the external dielectric layer 20 and located at least 5 ?m away from an internal electrode layer 3a, arranged outermost part of all the internal electrode layers, to the stacked direction, and x is thickness of the internal dielectric layer 2, y1 and x satisfy the following equations, y1??0.75x+2.275 and y1??0.75x+1.675.

Abstract: A multilayer ceramic capacitor 1 having internal electrode layers 3 and internal dielectric layers 2 having thickness of at most 3.5 ?m wherein; the internal dielectric layers 2 comprising dielectric particles contacting the internal electrode layers (contacting dielectric particles 2a) and dielectric particles not contacting the internal electrode layers (non-contacting dielectric particles 2b), and when an average particle size of an entire plural number of dielectric particles included in the internal dielectric layers 2 is D50, and standard deviation for particle size range of the contacting dielectric particles is ?, the multilayer ceramic capacitor satisfy the following equations; D50?0.25 ?m and ??0.14. According to the present invention, multilayer ceramic capacitor 1 is provided wherein the capacitor is expected to have improved DC bias characteristic even when the internal dielectric layers 2 are made thinner.

Abstract: There is provided a multilayer ceramic capacitor 1, having an internal electrode layer 3 and an interlayer dielectric layer 2 having a thickness of 3.5 ?m or less, wherein the interlayer dielectric layer 2 is composed of contact dielectric particles 2a contacting said internal electrode layer and noncontact dielectric particles 2b not contacting said internal electrode layer; and when assuming that an average particle diameter of the contact dielectric particles 2a is D50e and an average particle diameter of the noncontact dielectric particles 2b is D50d, D50e<0.450 ?m and (D50e/D50d)=1.20 to 3.00 (note that 1.20 and 3.00 are excluded) are satisfied, wherein an improvement of a bias characteristic at 85° C. can be expected even when the interlayer dielectric layer 2 is made thin.