Abstract: A lead frame includes a plurality of lead portions. At least a part of an upper surface of the lead portion and a sidewall surface of the lead portion is a rough surface having been subjected to roughening treatment. A value of a* in a CIELab color space of the rough surface is within a range from 12 to 19, and a value of b* is within a range from 12 to 17.

Abstract: A lead frame includes a plurality of lead portions. At least a part of an upper surface of the lead portion and a sidewall surface of the lead portion is a rough surface having been subjected to roughening treatment. A value of a* in a CIELab color space of the rough surface is within a range from 12 to 19, and a value of b* is within a range from 12 to 17.

Abstract: A semiconductor circuit device comprises a first depletion type n-channel insulated gate field effect transistor (hereinafter referred to as IG-FET) having its gate and source electrodes connected to each other, a second depletion type n-channel IG-FET connected between the source electrode of the first n-channel IG-FET and a positive power source and having its source and gate electrodes connected to each other, an enhancement type n-channel IG-FET connected between the source electrode of the first IG-FET and ground and having its gate electrode connected to an input terminal, an output terminal connected to the drain electrode of the first IG-FET, and a capacitor connected to the above-mentioned output terminal and ground. When a potential on the above-mentioned input terminal is dropped down to zero volt, the first depletion type IG-FET is abruptly shifted to the ON state, causing the capacitor to be abruptly charged by a positive power source.