Patents by Inventor Kazunori Takayanagi

Kazunori Takayanagi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5553252
    Abstract: A draw control chip and video chips V1-V4 are provided. They are connected by a 64-bit data bus, a 4-bit program signal line, and a 1-bit ready signal line. The video chip V1 comprises a decoder DEC1, a program buffer address register PBAR, a sequencer SEQ, a program buffer PB, a decoder DEC2, an address control unit, a selector SEL, and various registers. The video chip V1 and the video buffer APA1 are connected by the data bus. This system is used to transfer data from the control chip to the various video chips in a single operation. The 64-bit data bus can be divided into smaller sections allowing smaller segments of data to be simultaneously processed by the video chips. Additionally, the video chips are capable of providing data directly to one another without accessing the control chip.
    Type: Grant
    Filed: August 2, 1994
    Date of Patent: September 3, 1996
    Assignee: International Business Machines Corporation
    Inventors: Kazunori Takayanagi, Shinpei Watanabe
  • Patent number: 5502801
    Abstract: To rapidly draw straight lines and circular arcs of width 1 on a raster scan graphic display by determining whether or not the point, the X coordinate of which is incremented by 1 relative to the current point, and the point, the Y coordinate of which is incremented by 1 relative to the current point, are between the outlines f1 and f2 defining a straight line of width 1. If the point, the x coordinate of which is incremented by 1, is between the outlines f1 and f2, it is plotted and selected as the next pixel. If this is not the case, and the point, the y coordinate of which is incremented by 1, is between the outlines f1 and f2, it is plotted and selected as the next point. If neither point is between the outlines f1 and f2, the point, the x and y coordinates of which are incremented by 1, is plotted and selected as the next pixel.
    Type: Grant
    Filed: August 30, 1994
    Date of Patent: March 26, 1996
    Assignee: International Business Machines Corporation
    Inventors: Kazunori Takayanagi, Nobuyoshi Tanaka, Masaya Mori
  • Patent number: 5313227
    Abstract: A graphic display system capable of cutting out a partial image according to the invention includes image storage means, outline drawing means for drawing an outline of the partial image to be cut out, mask data generator means for generating mask data according to the outline, and partial image write means for writing into the image storage means only a portion of the source image which is not masked by the mask data. The image storage means is an all point addressable (APA) memory in which a source image storage area for storing the source image, a work storage area for storing a dot pattern representing the outline, and a destination storage areas for storing the partial image are allocated. The mask data generator means generates mask data, whereby a region enclosed with the outline dot pattern is put in the non-masked state, while the rest is put in the masked state.
    Type: Grant
    Filed: September 9, 1993
    Date of Patent: May 17, 1994
    Assignee: International Business Machines Corporation
    Inventors: Yutaka Aoki, Kazunori Takayanagi