Patents by Inventor Kazunori Tanimoto
Kazunori Tanimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8867010Abstract: A display panel has a plurality of gate terminals that are formed of a gate metal layer and a plurality of source terminals that are formed of a source metal layer, disposed alternately as seen in a plane. From each of the source terminals an intermediate region and a terminal region are provided with inorganic insulating film such that a source terminal lead formed of the source metal layer is covered therewith. The intermediate region is provided with organic insulating film such that the inorganic insulating film is covered therewith. The inorganic insulating film is smaller in thickness in the terminal region than in the intermediate region. The inorganic insulating film has an opening in the terminal region to expose at least a portion of a surface of the source terminal.Type: GrantFiled: July 7, 2011Date of Patent: October 21, 2014Assignee: Sharp Kabushiki KaishaInventors: Isao Ogasawara, Tatsuji Saitoh, Junichi Mori, Katsuya Ogawa, Kazunori Tanimoto
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Patent number: 8653827Abstract: Provided is an active matrix substrate having improved display quality without forming an inspection line in a terminal arrangement region for inspecting short circuit between connection lines. Scanning lines (40) include first scanning lines having input ends for a scanning signal on one end side, and second scanning lines having input ends for a scanning signal the other end side. In a display region (4), the first scanning lines and the second scanning lines are formed alternately one by one. An active matrix substrate (2) includes a first inspection line (70) and a second inspection line (72) that cross each of a plurality of first connection lines (61), and a third inspection line (75) and a fourth inspection line (77) that cross each of a plurality of second connection lines (64). The first to the fourth inspection lines (70, 72, 75, 77) are formed in a frame-shaped wiring region (6), excluding the terminal arrangement region (5) and the display region (4).Type: GrantFiled: March 13, 2009Date of Patent: February 18, 2014Assignee: Sharp Kabushiki KaishaInventors: Kazunori Tanimoto, Isao Ogasawara, Masahiro Yoshida, Takehiko Kawamura, Hideaki Takizawa
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Publication number: 20130335684Abstract: A functional panel (FP) includes a COM substrate (4) and an SEG substrate (3) that face each other. The functional panel (FP) is combined with a display panel (LP) via an adhesive. The COM substrate (4), which is provided farther from the display panel (LP) than the SEG substrate (3) is, has edges (E1, E2) that face each other. The SEG substrate (3), which is provided closer to the display panel (LP) than the COM substrate (4) is, has (i) an edge (E3) provided along and inside the edge (E1) when viewed from above and (ii) an edge (E4) provided along and inside the edge (E2) when viewed from above. This effectively prevents the occurrence of a defective external shape.Type: ApplicationFiled: January 18, 2012Publication date: December 19, 2013Inventors: Kazuhiro Yoshikawa, Kazunori Tanimoto, Masayuki Tsuji, Takayuki Hayano, Nobuhiro Nakata, Yoshihiro Asai, Masahiro Yoshida, Tatsuji Saitoh, Isao Ogasawara
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Patent number: 8582068Abstract: An active matrix substrate is provided with first inspection wirings (70, 75) capable of inputting inspection signals to first switching wirings that are not adjacent to each other among the first switching wirings (69, 74) and to second switching wirings that are not adjacent to each other among the second switching wirings (69, 74), and second inspection wirings (72, 77) capable of inputting inspection signals to first switching wirings that are not adjacent to each other and not connected to the first inspection wirings among the first switching wirings (69, 74) and to second switching wirings that are not adjacent to each other and not connected to the first inspection wirings among the second switching wirings (69, 74).Type: GrantFiled: April 28, 2009Date of Patent: November 12, 2013Assignee: Sharp Kabushiki KaishaInventors: Takehiko Kawamura, Kazunori Tanimoto, Isao Ogasawara, Masahiro Yoshida, Hideaki Takizawa
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Patent number: 8558972Abstract: A liquid crystal display device includes a first substrate and a second substrate disposed to face each other, a polymer-dispersed liquid crystal layer provided between the first substrate and the second substrate, and a black matrix provided on the first substrate, where a display region for displaying an image and a frame region around the display region are defined, and in the frame region, the black matrix includes a plurality of light-blocking regions spaced apart from one another.Type: GrantFiled: October 30, 2009Date of Patent: October 15, 2013Assignee: Sharp Kabushiki KaishaInventors: Yasushi Asaoka, Eiji Satoh, Kazuhiro Deguchi, Sayuri Fujiwara, Takafumi Matsuda, Katsuhiro Mikumo, Kazunori Tanimoto
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Publication number: 20130155345Abstract: A display panel has a plurality of gate terminals that are formed of a gate metal layer and a plurality of source terminals that are formed of a source metal layer, disposed alternately as seen in a plane. From each of the source terminals an intermediate region and a terminal region are provided with inorganic insulating film such that a source terminal lead formed of the source metal layer is covered therewith. The intermediate region is provided with organic insulating film such that the inorganic insulating film is covered therewith. The inorganic insulating film is smaller in thickness in the terminal region than in the intermediate region. The inorganic insulating film has an opening in the terminal region to expose at least a portion of a surface of the source terminal.Type: ApplicationFiled: July 7, 2011Publication date: June 20, 2013Applicant: Sharp Kabushiki KaishaInventors: Isao Ogasawara, Tatsuji Saitoh, Junichi Mori, Katsuya Ogawa, Kazunori Tanimoto
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Patent number: 8400597Abstract: Each of picture elements (14) has a plurality of alignment regions (R1, R2, R3, and R4), in each of which liquid crystal molecules contained in a liquid crystal layer are aligned in a direction that is different from those in the others of the plurality of alignment regions. Each of a plurality of scanning signal lines (32) and a border region (R11 and R12) between corresponding adjacent ones of the plurality of alignment regions (R1, R2, R3, and R4) at least partially overlap each other when viewed from above.Type: GrantFiled: March 27, 2009Date of Patent: March 19, 2013Assignee: Sharp Kabushiki KaishaInventors: Junichi Morinaga, Katsushige Asada, Masahiro Yoshida, Tetsuya Fujikawa, Katsuhiro Mikumo, Kuniko Maeno, Ryohki Itoh, Satoshi Horiuchi, Tatsuji Saitoh, Isao Ogasawara, Kazunori Tanimoto, Katsuhiro Okada, Toshiaki Fujihara, Masakatsu Tominaga
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Patent number: 8330691Abstract: A dummy line, which is disposed in a dummy pixel region (2) on the side of a test wiring region (1) and which has a parasitic capacitance effect like that of an adjacent scanning line (Gj) in an effective display region (3), is commonly used as a test switch line (1a). This test switch line (1a) is provided away from a dummy scanning line (DG) by intervals at which the scanning lines (Gj) are provided in the effective display region (3). As a result, it is possible to realize a display panel capable of reducing a frame area while keeping a test circuit region and the dummy pixel region in the frame area, and a display device having the display panel.Type: GrantFiled: April 11, 2007Date of Patent: December 11, 2012Assignee: Sharp Kabushiki KaishaInventors: Kazunori Tanimoto, Junichi Morinaga
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Patent number: 8274464Abstract: A plurality of source lines extending parallel to each other while alternately turning between a plurality of pixel electrodes provided in a delta arrangement, each have a plurality of first linear portions each extending along a side of the corresponding pixel electrode, a plurality of second linear portions each linked to the corresponding first linear portion and extending along a side of the corresponding pixel electrode to a middle portion of the side, and a plurality of protruding portions each extending from one end of the corresponding second linear portion along a side of the corresponding pixel electrode.Type: GrantFiled: September 8, 2008Date of Patent: September 25, 2012Assignee: Sharp Kabushiki KaishaInventors: Isao Asako, Junichi Morinaga, Sunao Aoki, Kazunori Tanimoto
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Publication number: 20120002142Abstract: A liquid crystal display device includes a first substrate and a second substrate disposed to face each other, a polymer-dispersed liquid crystal layer provided between the first substrate and the second substrate, and a black matrix provided on the first substrate, where a display region for displaying an image and a frame region around the display region are defined, and in the frame region, the black matrix includes a plurality of light-blocking regions spaced apart from one another.Type: ApplicationFiled: October 30, 2009Publication date: January 5, 2012Applicant: SHARP KABUSHIKI KAISHAInventors: Yasushi Asaoka, Eiji Satoh, Kazuhiro Deguchi, Sayuri Fujiwara, Takafumi Matsuda, Katsuhiro Mikumo, Kazunori Tanimoto
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Publication number: 20110075087Abstract: Each of picture elements (14) has a plurality of alignment regions (R1, R2, R3, and R4), in each of which liquid crystal molecules contained in a liquid crystal layer are aligned in a direction that is different from those in the others of the plurality of alignment regions. Each of a plurality of scanning signal lines (32) and a border region (R11 and R12) between corresponding adjacent ones of the plurality of alignment regions (R1, R2, R3, and R4) at least partially overlap each other when viewed from above.Type: ApplicationFiled: March 27, 2009Publication date: March 31, 2011Inventors: Junichi Morinaga, Katsushige Asada, Masahiro Yoshida, Tetsuya Fujikawa, Katsuhiro Mikumo, Kuniko Maeno, Ryohki Itoh, Satoshi Horiuchi, Tatsuji Saitoh, Isao Ogasawara, Kazunori Tanimoto, Katsuhiro Okada, Toshiaki Fujihara, Masakatsu Tominaga
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Publication number: 20110018142Abstract: An active matrix substrate is provided with first inspection wirings (70, 75) capable of inputting inspection signals to first switching wirings that are not adjacent to each other among the first switching wirings (69, 74) and to second switching wirings that are not adjacent to each other among the second switching wirings (69, 74), and second inspection wirings (72, 77) capable of inputting inspection signals to first switching wirings that are not adjacent to each other and not connected to the first inspection wirings among the first switching wirings (69, 74) and to second switching wirings that are not adjacent to each other and not connected to the first inspection wirings among the second switching wirings (69, 74).Type: ApplicationFiled: April 28, 2009Publication date: January 27, 2011Inventors: Takehiko Kawamura, Kazunori Tanimoto, Isao Ogasawara, Masahiro Yoshida, Hideaki Takizawa
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Publication number: 20110006780Abstract: Provided is an active matrix substrate having improved display quality without forming an inspection line in a terminal arrangement region for inspecting short circuit between connection lines. Scanning lines (40) include first scanning lines having input ends for a scanning signal on one end side, and second scanning lines having input ends for a scanning signal the other end side. In a display region (4), the first scanning lines and the second scanning lines are formed alternately one by one. An active matrix substrate (2) includes a first inspection line (70) and a second inspection line (72) that cross each of a plurality of first connection lines (61), and a third inspection line (75) and a fourth inspection line (77) that cross each of a plurality of second connection lines (64). The first to the fourth inspection lines (70, 72, 75, 77) are formed in a frame-shaped wiring region (6), excluding the terminal arrangement region (5) and the display region (4).Type: ApplicationFiled: March 13, 2009Publication date: January 13, 2011Inventors: Kazunori Tanimoto, Isao Ogasawara, Masahiro Yoshida, Takehiko Kawamura, Hideaki Takizawa
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Patent number: 7847577Abstract: By feeding inspection signals independent from each other to upper first and second gate lead inspection lines (52b, 52c), respectively, while maintaining the upper gate-side switching elements (40c) in an ON state, any short circuit between adjacent gate lines (40) of upper gate lines (40) and the like can be detected. By feeding inspection signals independent from each other to lower first and second gate lead inspection lines (53b, 53c), respectively, while maintaining lower gate-side switching elements (40c?) in an ON state, any short circuit between adjacent gate lines (40) of lower gate lines (40) and the like can be detected. By feeding inspection signals independent from each other to source lead inspection lines (55) while maintaining source-side switching elements (41) in an ON state, any short circuit between adjacent ones of source lines (41) and the like can be detected.Type: GrantFiled: March 12, 2007Date of Patent: December 7, 2010Assignee: Sharp Kabushiki KaishaInventors: Masahiro Yoshida, Kazunori Tanimoto, Yasuhiro Mimura
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Publication number: 20100245223Abstract: A plurality of source lines extending parallel to each other while alternately turning between a plurality of pixel electrodes provided in a delta arrangement, each have a plurality of first linear portions each extending along a side of the corresponding pixel electrode, a plurality of second linear portions each linked to the corresponding first linear portion and extending along a side of the corresponding pixel electrode to a middle portion of the side, and a plurality of protruding portions each extending from one end of the corresponding second linear portion along a side of the corresponding pixel electrode.Type: ApplicationFiled: September 8, 2008Publication date: September 30, 2010Inventors: Isao Asako, Junichi Morinaga, Sunao Aoki, Kazunori Tanimoto
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Publication number: 20100006838Abstract: By feeding inspection signals independent from each other to upper first and second gate lead inspection lines (52b, 52c), respectively, while maintaining the upper gate-side switching elements (40c) in an ON state, any short circuit between adjacent gate lines (40) of upper gate lines (40) and the like can be detected. By feeding inspection signals independent from each other to lower first and second gate lead inspection lines (53b, 53c), respectively, while maintaining lower gate-side switching elements (40c?) in an ON state, any short circuit between adjacent gate lines (40) of lower gate lines (40) and the like can be detected. By feeding inspection signals independent from each other to source lead inspection lines (55) while maintaining source-side switching elements (41) in an ON state, any short circuit between adjacent ones of source lines (41) and the like can be detected.Type: ApplicationFiled: March 12, 2007Publication date: January 14, 2010Inventors: Masahiro Yoshida, Kazunori Tanimoto, Yasuhiro Mimura
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Patent number: 7612834Abstract: A parallax barrier is manufactured by forming a light-blocking layer by patterning a metal layer or a resin layer on a barrier glass in a photolithography step. On a mask used in the photolithography step, some pitches between slits are different, the slits corresponding to portions whereupon the light-blocking layers are to be formed. In addition, on the mask, first pitches (for instance, 100) and second pitches (for instance 99.5), which can be actually formed with accuracy, are formed in a cycle, and the average of such pitches can be accord with a theoretical pitch distance (for instance, 99.99). Thus, in the parallax barrier to be used for a multiple display device, visibility of the entire screen can be improved, and the parallax barrier which can be manufactured by using the mask lithography technology having a limited accuracy, and a method for manufacturing such parallax barrier are provided.Type: GrantFiled: June 26, 2006Date of Patent: November 3, 2009Assignee: Sharp Kabushiki KaishaInventors: Kazunori Tanimoto, Tatsuji Saitoh
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Publication number: 20090231255Abstract: A dummy line, which is disposed in a dummy pixel region (2) on the side of a test wiring region (1) and which has a parasitic capacitance effect like that of an adjacent scanning line (Gj) in an effective display region (3), is commonly used as a test switch line (1a). This test switch line (1a) is provided away from a dummy scanning line (DG) by intervals at which the scanning lines (Gj) are provided in the effective display region (3). As a result, it is possible to realize a display panel capable of reducing a frame area while keeping a test circuit region and the dummy pixel region in the frame area, and a display device having the display panel.Type: ApplicationFiled: April 11, 2007Publication date: September 17, 2009Inventors: Kazunori Tanimoto, Junichi Morinaga
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Publication number: 20090080099Abstract: A parallax barrier is manufactured by forming a light-blocking layer by patterning a metal layer or a resin layer on a barrier glass in a photolithography step. On a mask used in the photolithography step, some pitches between slits are different, the slits corresponding to portions whereupon the light-blocking layers are to be formed. In addition, on the mask, first pitches (for instance, 100) and second pitches (for instance 99.5), which can be actually formed with accuracy, are formed in a cycle, and the average of such pitches can be accord with a theoretical pitch distance (for instance, 99.99). Thus, in the parallax barrier to be used for a multiple display device, visibility of the entire screen can be improved, and the parallax barrier which can be manufactured by using the mask lithography technology having a limited accuracy, and a method for manufacturing such parallax barrier are provided.Type: ApplicationFiled: June 26, 2006Publication date: March 26, 2009Applicant: Sharp Kabushiki KaishaInventors: Kazunori Tanimoto, Tatsuji Saitoh