Patents by Inventor Kazuo Aizawa

Kazuo Aizawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240213251
    Abstract: According to one or more embodiments of the disclosure, an apparatus comprising a pad above a semiconductor substrate, an n-well in the semiconductor substrate, and a floating p-well in the semiconductor substrate is provided. The floating p-well is below the pad and surrounded by the n-well in the semiconductor substrate.
    Type: Application
    Filed: November 28, 2023
    Publication date: June 27, 2024
    Applicant: Micron Technology, Inc.
    Inventors: Akiyoshi Seko, Yu Kosuge, Takahiro Sonoda, Kazuo Aizawa, Koji Hamada
  • Publication number: 20130248809
    Abstract: As for a variable resistive element including first and second electrodes, and a variable resistor containing a metal oxide between the first and second electrodes, in a case where a current path having a locally high current density of a current flowing between the both electrodes is formed in the metal oxide, and resistivity of at least one specific electrode having higher resistivity of the both electrodes is 100 ??cm or more, a dimension of a contact region of the specific electrode with the variable resistor in a short side or short axis direction is set to be more than 1.4 times as long as a film thickness of the specific electrode, which reduces variation in parasitic resistance generated in an electrode part due to process variation of the electrode, and prevents variation in resistance change characteristics of the variable resistive element generated due to the variation in parasitic resistance.
    Type: Application
    Filed: March 22, 2013
    Publication date: September 26, 2013
    Applicants: ELPIDA MEMORY, INC., SHARP KABUSHIKI KAISHA
    Inventors: Yukio TAMAI, Takashi NAKANO, Nobuyoshi AWAYA, Kazuo AIZAWA, Isamu ASANO, Naoya HIGANO, Tsuyoshi KAWAGOE
  • Patent number: 8335106
    Abstract: To include a superlattice laminate having laminated thereon a first crystal layer of which crystal lattice is a cubic crystal and in which positions of constituent atoms are reversibly replaced by application of energy, and a second crystal layer having a composition different from that of the first crystal layer, and an orientation layer that is an underlaying layer of the superlattice laminate and causes a laminated surface of the first crystal layer to be (111)-orientated. According to the present invention, the laminated surface of the first crystal layer can be (111)-orientated by using the orientation layer as an underlaying layer. In the first crystal layer of which laminated surface is (111)-orientated, a crystal structure reversibly changes when a relatively low energy is applied. Therefore, characteristics of a superlattice device having this crystal layer can be enhanced.
    Type: Grant
    Filed: May 3, 2010
    Date of Patent: December 18, 2012
    Assignee: Elpida Memory, Inc.
    Inventors: Kazuo Aizawa, Isamu Asano, Junji Tominaga, Alexander Kolobov, Paul Fons, Robert Simpson
  • Patent number: 8295080
    Abstract: A solid-state memory device includes: a superlattice laminate having plural crystal layers laminated therein, the crystal layers including first and second crystal layers having mutually opposite compositions; a lower electrode provided on a first surface in a laminating direction of the superlattice laminate; and an upper electrode provided on a second surface of the superlattice laminate in the laminating direction. The first crystal layer included in the superlattice laminate is made of a phase change compound. According to the present invention, the superlattice laminate laminated in opposite directions of the upper and lower electrodes is sandwiched between these electrodes. Therefore, when an electric energy is applied to the superlattice laminate via these electrodes, a uniform electric energy can be applied to a laminated surface of the superlattice laminate. Accordingly, fluctuation of a resistance is small even when information is repeatedly rewritten, and data can be read stably as a result.
    Type: Grant
    Filed: June 4, 2010
    Date of Patent: October 23, 2012
    Assignee: Elpida Memory, Inc.
    Inventors: Kazuo Aizawa, Isamu Asano, Junji Tominaga, Alexander Kolobov, Paul Fons, Robert Simpson
  • Publication number: 20100315867
    Abstract: A solid-state memory device includes: a superlattice laminate having plural crystal layers laminated therein, the crystal layers including first and second crystal layers having mutually opposite compositions; a lower electrode provided on a first surface in a laminating direction of the superlattice laminate; and an upper electrode provided on a second surface of the superlattice laminate in the laminating direction. The first crystal layer included in the superlattice laminate is made of a phase change compound. According to the present invention, the superlattice laminate laminated in opposite directions of the upper and lower electrodes is sandwiched between these electrodes. Therefore, when an electric energy is applied to the superlattice laminate via these electrodes, a uniform electric energy can be applied to a laminated surface of the superlattice laminate. Accordingly, fluctuation of a resistance is small even when information is repeatedly rewritten, and data can be read stably as a result.
    Type: Application
    Filed: June 4, 2010
    Publication date: December 16, 2010
    Applicant: ELPIDA MEMORY, INC
    Inventors: Kazuo AIZAWA, Isamu ASANO, Junji TOMINAGA, Alexander KOLOBOV, Paul FONS, Robert SIMPSON
  • Publication number: 20100284218
    Abstract: To include a superlattice laminate having laminated thereon a first crystal layer of which crystal lattice is a cubic crystal and in which positions of constituent atoms are reversibly replaced by application of energy, and a second crystal layer having a composition different from that of the first crystal layer, and an orientation layer that is an underlaying layer of the superlattice laminate and causes a laminated surface of the first crystal layer to be (111)-orientated. According to the present invention, the laminated surface of the first crystal layer can be (111)-orientated by using the orientation layer as an underlaying layer. In the first crystal layer of which laminated surface is (111)-orientated, a crystal structure reversibly changes when a relatively low energy is applied. Therefore, characteristics of a superlattice device having this crystal layer can be enhanced.
    Type: Application
    Filed: May 3, 2010
    Publication date: November 11, 2010
    Applicant: Elpida Memory, Inc.
    Inventors: Kazuo AIZAWA, Isamu Asano, Junji Tominaga, Alexander Kolobov, Paul Fons, Robert Simpson
  • Patent number: 6225227
    Abstract: In a method for manufacturing a semiconductor device in a wafer having a device formation area and an inspection pattern formation area, an interconnection layer is formed in the device formation area with forming no interconnection layer in the inspection pattern formation area. An interlayer insulating film is formed to cover the whole surface, and then, is selectively removed to form a first hole exposing a portion of the interconnection layer in the device formation area and a second hole exposing a portion of a silicon layer in the inspection pattern formation area. An aluminum-based alloy is filed into the first and second holes. In the second hole, spiking occurs into the silicon layer when aluminum from the aluminum-based alloy comes in contact with the silicon layer. After filling, the surface above the second hole is observed for an indication that spiking occurred into the silicon layer.
    Type: Grant
    Filed: April 17, 1998
    Date of Patent: May 1, 2001
    Assignee: NEC Corporation
    Inventor: Kazuo Aizawa
  • Patent number: 6124190
    Abstract: In a method of manufacturing a semiconductor integrated circuit, a gate structure with sidewall insulating films and a field oxidation film are formed on a semiconductor substrate. Then, diffusion layers are formed for the gate structure with the sidewall insulating films. Subsequently, a surface layer is removed from each of the sidewall insulating films and the field oxidation film. Next, a silicide layer is formed in a surface layer of each of the diffusion layers in self-alignment with the gate structure with the sidewall insulating films and the field oxidation film.
    Type: Grant
    Filed: December 11, 1997
    Date of Patent: September 26, 2000
    Assignee: NEC Corporation
    Inventors: Yoshiaki Yamamoto, Kazuo Aizawa
  • Patent number: 5985754
    Abstract: In a method of forming a wiring layer, a connection hole is formed to penetrate an insulating film. A barrier metal film is formed at least on an inner wall of the connection hole and a peripheral portion to have surface roughness. Next, a film of the metal including aluminum is deposited on the barrier metal film to fill a portion of the connection hole. Then, while the metal including aluminum is flowed into the connection hole, the film of the metal including aluminum is further deposited to fill the remaining portion of the connection hole with the metal including aluminum. In order to have the surface roughness sufficient to prevent cohesion of particles of metal including aluminum, the barrier metal film may be formed as an immediately lower layer of the metal film at a temperature in a range of room temperature to 150.degree. C. or under a pressure in a range of 10 to 30 mTorr.
    Type: Grant
    Filed: December 13, 1996
    Date of Patent: November 16, 1999
    Assignee: NEC Corporation
    Inventor: Kazuo Aizawa
  • Patent number: 4037033
    Abstract: An improved rechargeable nickel-zinc battery is described which is capable of undergoing many charge-discharge cycles (cycle life), with deep discharge, and of high performance with heavy drain discharge during use. The increased cycle life is accomplished by a suitable combination of electrochemical generating elements. The high performance with heavy drain discharge service is obtained by an improved zinc electrode construction. The battery of this invention has a sheet-like kneaded zinc electrode, a sheet-like nickel oxide electrode with limited capacity ratio thereof, a separator, an electrolyte absorber, and a concentrated alkaline electrolyte in limited amounts.
    Type: Grant
    Filed: January 20, 1976
    Date of Patent: July 19, 1977
    Assignee: Tokyo Shibaura Electric Co. Ltd.
    Inventors: Tsutomu Takamura, Tamotsu Shirogami, Hirokazu Niki, Kazuo Aizawa