Abstract: A microcomputer for an IC card arranged so that only a user mode can be performed after the microcomputer has been shipped to a user. Data representing that the microcomputer has been shipped is written at the time of shipment in a test region of an EEPROM. A shipment confirmation routine for confirming whether the shipment data has been written is performed before execution of a branch routine for branching to other programs in accordance with an executed command supplied from outside the microcomputer. If the shipment data has been written in the test region of the EEPROM as confirmed in the shipment confirmation routine, only branching to the user mode is permitted.

Abstract: An EEPROM apparatus being provided with, in an ECC circuit (6), an ECC code generating unit (19) which automatically generates "5(H)" ((H) represents hexadecimal number), that is, "0101(B)" ((B) represents binary number) as the ECC code when data, in which head is 37 1" and thereafter "0" and "1" are repeated in binary notation, for example, "55(H)", that is, "01010101(B)" is written, as the data to be stored in an EEPROM 50, and automatically generates "A(H)", that is, "1010(B)" as the ECC code when data, in which head is "0" and thereafter "1" and "0" are repeated in binary notation, for example, "AA(H)", that is, "10101010(B)" is written, and capable of executing checker pattern test easily and in a short time.

Abstract: In a memory unit having a sense amplifier for reading data, the dependence of the memory cell current detection level of the sense amplifier on the power source voltage is restrained. A memory-unit sense amplifier includes a bias circuit (20, 21, 22) for generating an output which mitigates fluctuations in the power source voltage VDD; and a detection result output section (10, 15) which outputs a memory cell current detection result obtained for the purpose of obtaining the value of memory cell data and which has a Pch (P-channel transistor), to the gate of which the output of the bias circuit (20, 21, 22) is connected, whereby fluctuations in the source/gate voltage of the Pch 10 are mitigated so as to restrain the dependence of the memory cell current detection level on the power source voltage.

Abstract: This invention relates to an automation system for nuclear power plants. This system comprises operation plan making means, supervisory control means, and control means for controlling controlled objects. The operation plan making means makes a new operation plan to restore a normal operating condition which existed before the plant condition deviated from the normal operation range. The supervisory control means outputs control commands according to an operation plan under abnormal condition when the plant operating condition deviates from the normal operation range. Furthermore, the supervisory control means outputs control commands according a new operation plan prepared by the operation plan making means after an operation according to an operation plan under abnormal condition has been finished. The control means for controlling controlled objects controls the controlled objects according to control commands output from the supervisory control means.

Abstract: An IC card includes a CPU for processing data, a data receiving circuit for receiving data and inputting the data to the CPU, a data transmitting circuit for transmitting data from the CPU, a reset receiving device for receiving an external reset signal, a monitor timer for generating a timer reset signal when there is no response after a prescribed time has elapsed following receipt of data by the data receiving circuit, and a discrimination circuit for determining which of the external reset signal or a timer reset signal from the monitor timer has been received, holding the determination, and resetting the CPU in response to a reset signal.

Abstract: A non-contact type information card includes a modulating/demodulating circuit, an antenna circuit, a CPU, a RAM, and a clock signal generating circuit. In the non-contact type information card, when the modulating/demodulating circuit receives a new command signal, the CPU determines whether first and second identification information in the new command signal agrees with the first and second identification information in an old command signal. When the first and second identification information of the new command signal agree with that of the old command signal, the CPU stops the operation of the clock generating circuit until the next command signal is received.

Abstract: A digital facsimile communication control method includes a step of selectively determining a data communication mode between a digital circuit switching mode and a packet switching mode. When the digital circuit switching mode has been selected, while optically reading an original to be transmitted, the amount of data stored for transmission is checked and also the time is checked. And, if the amount of data stored for transmission has reached a predetermined amount before the time has reached a predetermined time, the amount of data stored for transmission is formed into a frame of data, which is then transmitted. On the other hand, if the time has reached the predetermined time before the amount of data stored for transmission has reached the predetermined amount, an amount of data which has so far been stored is formed into a frame of data, which is then transmitted.

Abstract: This is a multiplexing control unit comparing a plurality of subsystems completely separate and independent.Each subsystem is constituted as follows, and one objective device is controlled at the final stage output of the multiplexing control unit.A quantity or state of a plant is detected by a detector. A signal from the detector is output through a controller at each subsystem, and a normalcy decision signal for an output signal from the controller is output. A synthetic decision section selects one controller functioning most normally according to the normalcy decision signal of the output signal from the controller and outputs a control signal corresponding to the selected controller. An output signal switching section selects an output for the controller functioning most normally according to the control signal from the synthetic decision division to output to a device to be controlled.