Patents by Inventor Kazuo Hashimi
Kazuo Hashimi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11075140Abstract: The disclosure provides a heat conduction structure with higher heat conductivity. This embodiment is a heat conduction structure where heat is conducted from a first member to a second member. The heat conduction structure includes at least one self-assembled monolayer and a heat dissipation grease. The self-assembled monolayer is formed on at least one surface of the first member and the second member. The heat dissipation grease is disposed between the first member and the second member. The heat dissipation grease is in contact with the self-assembled monolayer.Type: GrantFiled: June 24, 2019Date of Patent: July 27, 2021Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, NATIONAL UNIVERSITY CORPORATION NAGOYA UNIVERSITYInventors: Takeshi Bessho, Masataka Deguchi, Nagahiro Saito, Kazuo Hashimi
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Publication number: 20200006195Abstract: The disclosure provides a heat conduction structure with higher heat conductivity. This embodiment is a heat conduction structure where heat is conducted from a first member to a second member. The heat conduction structure includes at least one self-assembled monolayer and a heat dissipation grease. The self-assembled monolayer is formed on at least one surface of the first member and the second member. The heat dissipation grease is disposed between the first member and the second member. The heat dissipation grease is in contact with the self-assembled monolayer.Type: ApplicationFiled: June 24, 2019Publication date: January 2, 2020Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, NATIONAL UNIVERSITY CORPORATION NAGOYA UNIVERSITYInventors: Takeshi BESSHO, Masataka DEGUCHI, Nagahiro SAITO, Kazuo HASHIMI
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Semiconductor device with inverted trapezoidal cross sectional profile in surface areas of substrate
Patent number: 8809919Abstract: A semiconductor device fabrication method includes the steps of (a) forming a dielectric film on a semiconductor substrate; (b) etching the dielectric film by a dry process; and (c) supplying thermally decomposed atomic hydrogen onto the semiconductor substrate under a prescribed temperature condition, to remove a damaged layer produced in the semiconductor substrate due to the dry process.Type: GrantFiled: January 11, 2012Date of Patent: August 19, 2014Assignee: Fujitsu Semiconductor LimitedInventors: Kazuo Hashimi, Hidekazu Sato -
Patent number: 8685265Abstract: An etching apparatus includes a process unit and a control unit. Emission intensity of plasma inside the process unit is obtained by an OES detector, a nonlinear regression analysis is performed by an etching control device to determine a regression formula. The nonlinear regression analysis is performed by using the emission intensity of the plasma obtained until a first time when the emission intensity of the plasma passes a peak, and a second time to be an etching end point is calculated by using the regression formula. The etching end point is calculated as a time when the emission intensity decreases for a predetermined value from the first time. The etching apparatus finishes an etching when the process reaches the etching end point. It is thereby possible to control the etching end point with high-accuracy.Type: GrantFiled: May 11, 2012Date of Patent: April 1, 2014Assignee: Fujitsu Semiconductor LimitedInventors: Yoshiyuki Nakao, Kazuo Hashimi
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Patent number: 8592951Abstract: A method of manufacturing a semiconductor device forms the semiconductor device in a device region of a semiconductor substrate simultaneously with forming a monitor semiconductor device that includes a gate electrode made of silicon containing material arranged on a gate insulating film in a monitor region of the semiconductor substrate, a source electrode and a drain electrode formed on the semiconductor substrate on corresponding sides of the gate electrode. The gate electrode is removed without removing a gate insulating film by applying pyrolysis hydrogen generated by pyrolysis on the monitor semiconductor device in the monitor region, and the gate insulating film is removed by a wet process. Impurities distribution of a silicon active region appearing after the gate electrode is removed is measured and fed back to a semiconductor manufacturing process.Type: GrantFiled: March 26, 2012Date of Patent: November 26, 2013Assignee: Fujitsu Semiconductor LimitedInventors: Kazuo Hashimi, Hidekazu Sato
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Publication number: 20120288969Abstract: An etching apparatus includes a process unit and a control unit. Emission intensity of plasma inside the process unit is obtained by an OES detector, a nonlinear regression analysis is performed by an etching control device to determine a regression formula. The nonlinear regression analysis is performed by using the emission intensity of the plasma obtained until a first time when the emission intensity of the plasma passes a peak, and a second time to be an etching end point is calculated by using the regression formula. The etching end point is calculated as a time when the emission intensity decreases for a predetermined value from the first time. The etching apparatus finishes an etching when the process reaches the etching end point. It is thereby possible to control the etching end point with high-accuracy.Type: ApplicationFiled: May 11, 2012Publication date: November 15, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Yoshiyuki Nakao, Kazuo Hashimi
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Publication number: 20120181671Abstract: A method of manufacturing a semiconductor device forms the semiconductor device in a device region of a semiconductor substrate simultaneously with forming a monitor semiconductor device that includes a gate electrode made of silicon containing material arranged on a gate insulating film in a monitor region of the semiconductor substrate, a source electrode and a drain electrode formed on the semiconductor substrate on corresponding sides of the gate electrode. The gate electrode is removed without removing a gate insulating film by applying pyrolysis hydrogen generated by pyrolysis on the monitor semiconductor device in the monitor region, and the gate insulating film is removed by a wet process. Impurities distribution of a silicon active region appearing after the gate electrode is removed is measured and fed back to a semiconductor manufacturing process.Type: ApplicationFiled: March 26, 2012Publication date: July 19, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Kazuo Hashimi, Hidekazu Sato
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Publication number: 20120104477Abstract: A semiconductor device fabrication method includes the steps of (a) forming a dielectric film on a semiconductor substrate; (b) etching the dielectric film by a dry process; and (c) supplying thermally decomposed atomic hydrogen onto the semiconductor substrate under a prescribed temperature condition, to remove a damaged layer produced in the semiconductor substrate due to the dry process.Type: ApplicationFiled: January 11, 2012Publication date: May 3, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Kazuo Hashimi, Hidekazu Sato
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Patent number: 8163572Abstract: A method of manufacturing a semiconductor device forms the semiconductor device in a device region of a semiconductor substrate simultaneously with forming a monitor semiconductor device that includes a gate electrode made of silicon containing material arranged on a gate insulating film in a monitor region of the semiconductor substrate, a source electrode and a drain electrode formed on the semiconductor substrate on corresponding sides of the gate electrode. The gate electrode is removed without removing a gate insulating film by applying pyrolysis hydrogen generated by pyrolysis on the monitor semiconductor device in the monitor region, and the gate insulating film is removed by a wet process. Impurities distribution of a silicon active region appearing after the gate electrode is removed is measured and fed back to a semiconductor manufacturing process.Type: GrantFiled: November 20, 2009Date of Patent: April 24, 2012Assignee: Fujitsu Semiconductor LimitedInventors: Kazuo Hashimi, Hidekazu Sato
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Patent number: 8114764Abstract: A semiconductor device fabrication method includes the steps of (a) forming a dielectric film on a semiconductor substrate; (b) etching the dielectric film by a dry process; and (c) supplying thermally decomposed atomic hydrogen onto the semiconductor substrate under a prescribed temperature condition, to remove a damaged layer produced in the semiconductor substrate due to the dry process.Type: GrantFiled: December 1, 2009Date of Patent: February 14, 2012Assignee: Fujitsu Semiconductor LimitedInventors: Kazuo Hashimi, Hidekazu Sato
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Patent number: 7691649Abstract: A method of stably and correctly evaluating impurities distribution under a gate of a semiconductor device without damaging a silicon substrate is disclosed. According to the evaluation method, a gate electrode made of a silicon containing material is removed without removing a gate insulating film by contacting pyrolysis hydrogen generated by pyrolysis to the semiconductor device that includes the gate electrode arranged on a semiconductor substrate through a gate insulating film, and a source electrode and a drain electrode formed on the semiconductor substrate on corresponding sides of the gate electrode. Further, a processed form of the gate is evaluated by observing a form of the gate insulating film that remains on the semiconductor substrate, the gate insulating film that remains on the semiconductor substrate is removed by a wet process, and the impurities distribution under the gate is measured and evaluated.Type: GrantFiled: April 21, 2006Date of Patent: April 6, 2010Assignee: Fujitsu Microelectronics LimitedInventors: Kazuo Hashimi, Hidekazu Sato
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Publication number: 20100072522Abstract: A semiconductor device fabrication method includes the steps of (a) forming a dielectric film on a semiconductor substrate; (b) etching the dielectric film by a dry process; and (c) supplying thermally decomposed atomic hydrogen onto the semiconductor substrate under a prescribed temperature condition, to remove a damaged layer produced in the semiconductor substrate due to the dry process.Type: ApplicationFiled: December 1, 2009Publication date: March 25, 2010Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Kazuo HASHIMI, Hidezaku SATO
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Publication number: 20100065947Abstract: A method of stably and correctly evaluating impurities distribution under a gate of a semiconductor device without damaging a silicon substrate is disclosed. According to the evaluation method, a gate electrode made of a silicon containing material is removed without removing a gate insulating film by contacting pyrolysis hydrogen generated by pyrolysis to the semiconductor device that includes the gate electrode arranged on a semiconductor substrate through a gate insulating film, and a source electrode and a drain electrode formed on the semiconductor substrate on corresponding sides of the gate electrode. Further, a processed form of the gate is evaluated by observing a form of the gate insulating film that remains on the semiconductor substrate, the gate insulating film that remains on the semiconductor substrate is removed by a wet process, and the impurities distribution under the gate is measured and evaluated.Type: ApplicationFiled: November 20, 2009Publication date: March 18, 2010Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Kazuo Hashimi, Hidekazu Sato
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Patent number: 7642192Abstract: A semiconductor device fabrication method includes the steps of (a) forming a dielectric film on a semiconductor substrate; (b) etching the dielectric film by a dry process; and (c) supplying thermally decomposed atomic hydrogen onto the semiconductor substrate under a prescribed temperature condition, to remove a damaged layer produced in the semiconductor substrate due to the dry process.Type: GrantFiled: April 26, 2005Date of Patent: January 5, 2010Assignee: Fujitsu Microelectronics LimitedInventors: Kazuo Hashimi, Hidekazu Sato
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Publication number: 20070138561Abstract: A method of stably and correctly evaluating impurities distribution under a gate of a semiconductor device without damaging a silicon substrate is disclosed. According to the evaluation method, a gate electrode made of a silicon containing material is removed without removing a gate insulating film by contacting pyrolysis hydrogen generated by pyrolysis to the semiconductor device that includes the gate electrode arranged on a semiconductor substrate through a gate insulating film, and a source electrode and a drain electrode formed on the semiconductor substrate on corresponding sides of the gate electrode. Further, a processed form of the gate is evaluated by observing a form of the gate insulating film that remains on the semiconductor substrate, the gate insulating film that remains on the semiconductor substrate is removed by a wet process, and the impurities distribution under the gate is measured and evaluated.Type: ApplicationFiled: April 21, 2006Publication date: June 21, 2007Applicant: FUJITSU LIMITEDInventors: Kazuo Hashimi, Hidekazu Sato
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Publication number: 20060006477Abstract: A semiconductor device fabrication method includes the steps of (a) forming a dielectric film on a semiconductor substrate; (b) etching the dielectric film by a dry process; and (c) supplying thermally decomposed atomic hydrogen onto the semiconductor substrate under a prescribed temperature condition, to remove a damaged layer produced in the semiconductor substrate due to the dry process.Type: ApplicationFiled: April 26, 2005Publication date: January 12, 2006Applicant: FUJITSU LIMITEDInventors: Kazuo Hashimi, Hidekazu Sato
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Patent number: 6528413Abstract: A semiconductor device comprises impurity diffusion layers formed in a semiconductor substrate and containing a metal element, whose siliciding activation energy is less than 1.8 eV, at a concentration of more than 1×1011 atoms/cm2 and less than 1×1015 atoms/cm2, an insulating film formed on the semiconductor substrate, contact holes formed in the insulating film on the impurity diffusion layers, and contact plugs formed via the contact holes. Accordingly, there is provided the semiconductor device that has a connection structure between an impurity-containing semiconductor layer and a conductive film and is capable of suppressing a leakage current generated at a contact portion between the impurity diffusion layer and the conductive film.Type: GrantFiled: September 25, 2001Date of Patent: March 4, 2003Assignee: Fujitsu LimitedInventor: Kazuo Hashimi
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Publication number: 20020177304Abstract: A semiconductor device comprises impurity diffusion layers formed in a semiconductor substrate and containing a metal element, whose siliciding activation energy is less than 1.8 eV, at a concentration of more than 1×1011 atoms/cm2 and less than 1×1015 atoms/cm2, an insulating film formed on the semiconductor substrate, contact holes formed in the insulating film on the impurity diffusion layers, and contact plugs formed via the contact holes. Accordingly, there is provided the semiconductor device that has a connection structure between an impurity-containing semiconductor layer and a conductive film and is capable of suppressing a leakage current generated at a contact portion between the impurity diffusion layer and the conductive film.Type: ApplicationFiled: September 25, 2001Publication date: November 28, 2002Applicant: Fujitsu LimitedInventor: Kazuo Hashimi
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Patent number: 5830807Abstract: A laminated structure formed by alternately laminating a silicon film and a silicon oxide film is successively etched in the same chamber. Two groups are selected from groups A, B, and C, the group A including NF.sub.3, CF.sub.4, and SF.sub.6, the group B including CO, CHF.sub.3, CH.sub.2 F.sub.2, C.sub.2 F.sub.6, C.sub.3 F.sub.8, and C.sub.4 F.sub.8, and the group C including Cl.sub.2, HBr, HCl and Br.sub.2. The laminated structure is etched by successively etching one of the silicon film and the silicon oxide film by a combination of gases having a first mixture ratio and the other by the combination of gases having a second mixture ratio different from the first mixture ratio, the combination of gases including at least one kind of gas selected from one group of the selected two groups and at least one kind of gas selected from the other group. A technology of manufacturing a semiconductor device is provided which can etch an alternate laminate efficiently with a simple system.Type: GrantFiled: May 30, 1997Date of Patent: November 3, 1998Assignee: Fujitsu LimitedInventors: Daisuke Matsunaga, Kazuo Hashimi, Genichi Komuro
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Patent number: 5322589Abstract: A process for recrystallizing a semiconductor layer including the steps of forming a polycrystalline or amorphous semiconductor layer on a substrate and scanning energy beam on the semiconductor layer, wherein the energy beam is vibrated substantially in parallel to the direction of advance of the scanning of the energy beam. For carrying out the process, the apparatus includes a sample stage for holding a sample having a polycrystalline or amorphous semiconductor layer, an energy beam source for generating energy beam, a scanning means for scanning the energy beam on the semiconductor layer, and a beam-vibrating means for vibrating the energy beam substantially in parallel to the direction of advance of the scanning of the energy beam.Type: GrantFiled: April 21, 1993Date of Patent: June 21, 1994Assignee: Fujitsu LimitedInventors: Hidesato Matsuoka, Kazuo Hashimi