Abstract: According to one embodiment, a semiconductor device includes: a semiconductor layer of a first conductivity type, and the semiconductor layer having a first and a second surfaces; a first conductive layer penetrating from the first surface side to the second surface side of the semiconductor layer; a first semiconductor region of a first conductivity type surrounding part of the first conductive layer on the second surface side of the semiconductor layer, a portion other than a front surface of the first semiconductor region being surrounded by the semiconductor layer; and a first insulating film provided between the first conductive layer and the semiconductor layer and between the first conductive layer and the first semiconductor region, a concentration of an impurity element contained in the first semiconductor region being higher than a concentration of an impurity element contained in the semiconductor layer.

Abstract: According to one embodiment, a semiconductor device includes: a semiconductor layer of a first conductivity type, the semiconductor layer having a first surface and a second surface on an opposite side to the first surface; a plurality of conductive layers extending in a direction from the first surface side toward the second surface side of the semiconductor layer; a first semiconductor region of a second conductivity type surrounding part of each of the plurality of conductive layers on the second surface side of the semiconductor layer, a portion other than a front surface of the first semiconductor region being surrounded by the semiconductor layer; and an insulating film provided between each of the plurality of conductive layers and the semiconductor layer and between each of the plurality of conductive layers and the first semiconductor region.

Abstract: According to one embodiment, a semiconductor device includes: a semiconductor layer of a first conductivity type, and the semiconductor layer having a first and a second surfaces; a first conductive layer penetrating from the first surface side to the second surface side of the semiconductor layer; a first semiconductor region of a first conductivity type surrounding part of the first conductive layer on the second surface side of the semiconductor layer, a portion other than a front surface of the first semiconductor region being surrounded by the semiconductor layer; and a first insulating film provided between the first conductive layer and the semiconductor layer and between the first conductive layer and the first semiconductor region, a concentration of an impurity element contained in the first semiconductor region being higher than a concentration of an impurity element contained in the semiconductor layer.

Abstract: According to one embodiment, a semiconductor device includes: a semiconductor layer of a first conductivity type, the semiconductor layer having a first surface and a second surface on an opposite side to the first surface; a plurality of conductive layers extending in a direction from the first surface side toward the second surface side of the semiconductor layer; a first semiconductor region of a second conductivity type surrounding part of each of the plurality of conductive layers on the second surface side of the semiconductor layer, a portion other than a front surface of the first semiconductor region being surrounded by the semiconductor layer; and an insulating film provided between each of the plurality of conductive layers and the semiconductor layer and between each of the plurality of conductive layers and the first semiconductor region.

Abstract: A memory includes a sense amplifier connected to one or more of bit lines and configured to sense data stored in the memory cells; and a word line driver configured to control a voltage of one or more of word lines. The memory cells constitute a memory block. The memory cells constitute a memory block being a unit of memory cells on which a data erasing operation is performed. A controller changes an erase condition during the data erasing operation performed on the memory block or a verify condition for a verify check of verifying whether the data has been erased from the memory cells in the memory block, in proportion to a ratio of number of predetermined logical value data to the data in the memory block or the page before the data erasing operation.

Abstract: A memory includes a sense amplifier connected to one or more of bit lines and configured to sense data stored in the memory cells; and a word line driver configured to control a voltage of one or more of word lines. The memory cells constitute a memory block. The memory cells constitute a memory block being a unit of memory cells on which a data erasing operation is performed. A controller changes an erase condition during the data erasing operation performed on the memory block or a verify condition for a verify check of verifying whether the data has been erased from the memory cells in the memory block, in proportion to a ratio of number of predetermined logical value data to the data in the memory block or the page before the data erasing operation.

Abstract: In a pattern layout which includes a first device pattern having a uniformly repeated pattern group having first lines and first spaces formed parallel to one anther and uniformly arranged with constant width at a constant pitch and a non-uniformly repeated pattern group having first lines and first spaces non-uniformly arranged, and a second device pattern arranged adjacent to the end portion of the non-uniformly repeated pattern group in an arrangement direction thereof and having second lines and second spaces whose widths are larger than the widths of the first lines and first spaces of the non-uniformly repeated pattern group, at least part of the widths of the first lines and the first spaces of the non-uniformly repeated pattern group is made larger than the width of the first line or the width of the first space of the uniformly repeated pattern group.

Abstract: A semiconductor device includes a semiconductor layer having a plurality of element regions in its surface area, which are delimited by at least one element isolation trench, a plurality of floating gate electrodes provided on the element regions with a first gate insulation film interposed therebetween and each including a first charge-storage layer having a first width which is equal to that of each of the element regions and a second charge-storage layer stacked on the first charge-storage layer and having a second width which is smaller than the first width, and a plurality of control gate electrodes provided on the floating gate electrodes with a second gate insulation films interposed therebetween. The device further includes an element isolating insulation film buried into the element isolation trench. The top surface of the element isolating insulation film is located higher than that of the first charge-storage layer.

Abstract: A semiconductor device includes a semiconductor layer having a plurality of element regions in its surface area, which are delimited by at least one element isolation trench, a plurality of floating gate electrodes provided on the element regions with a first gate insulation film interposed therebetween and each including a first charge-storage layer having a first width which is equal to that of each of the element regions and a second charge-storage layer stacked on the first charge-storage layer and having a second width which is smaller than the first width, and a plurality of control gate electrodes provided on the floating gate electrodes with a second gate insulation films interposed therebetween. The device further includes an element isolating insulation film buried into the element isolation trench. The top surface of the element isolating insulation film is located higher than that of the first charge-storage layer.

Abstract: In a pattern layout which includes a first device pattern having a uniformly repeated pattern group having first lines and first spaces formed parallel to one anther and uniformly arranged with constant width at a constant pitch and a non-uniformly repeated pattern group having first lines and first spaces non-uniformly arranged, and a second device pattern arranged adjacent to the end portion of the non-uniformly repeated pattern group in an arrangement direction thereof and having second lines and second spaces whose widths are larger than the widths of the first lines and first spaces of the non-uniformly repeated pattern group, at least part of the widths of the first lines and the first spaces of the non-uniformly repeated pattern group is made larger than the width of the first line or the width of the first space of the uniformly repeated pattern group.

Abstract: A semiconductor device includes a semiconductor layer having a plurality of element regions in its surface area, which are delimited by at least one element isolation trench, a plurality of floating gate electrodes provided on the element regions with a first gate insulation film interposed therebetween and each including a first charge-storage layer having a first width which is equal to that of each of the element regions and a second charge-storage layer stacked on the first charge-storage layer and having a second width which is smaller than the first width, and a plurality of control gate electrodes provided on the floating gate electrodes with a second gate insulation films interposed therebetween. The device further includes an element isolating insulation film buried into the element isolation trench. The top surface of the element isolating insulation film is located higher than that of the first charge-storage layer.

Abstract: The non-volatile semiconductor device includes a sub control gate in addition to the conventional structure having a control gate and a floating gate. When writing or erasing is performed, by applying various to the control gate and the sub control gate, the potential of the floating gate which is capacitively connected to the control and sub control gates is determined. Accordingly, the floating gate voltage is maintained at lower control voltage compared to conventional one by selecting larger coupling ratio. The sub control gate covering a part where charge concentration apt to occur avoids charge concentration and deterioration of the tunnel oxide film.

Abstract: A vehicle seat includes an outer skin layer, which covers the seat cushion or seat back. The seat cushion or seat back is integrally formed with a fastener disposed on a main surface portion thereof. The main surface portion has an underlayer disposed under an overlayer, which includes an outerskin surface, freely disposed over the underlayer. The overlayer and the underlayer are joined only along common edge portions thereof while the surface areas thereof are not attached. The lower side of the second underlayer is affixed to the fastener disposed on the seat cushion or seat back. Each of the skin layer and the overlayer and underlayer may be of two or three ply construction including a backing material and a wadding layer. This construction allows high assembly efficiency with a reduced number of parts. Further, disassembly of seat components for recycling is also simplified while enhanced appearance of the installed seat cover is easily accomplished.

Abstract: A crane provided with traveling wheels disposed under a crane frame. The crane includes a hoisting accessory which is adapted to be hoisted by a hoist apparatus. AC motors are provided as travel motors for driving the traveling wheels as well as hoist motors for driving the hoist apparatus. The crane is equipped with a DC power source generating DC power, inverter units converting the DC power into AC power and outputting the AC power, and a change-over or switching arrangement for supplying the AC power to the travel motors when the crane is being moved and to the hoist motors during a hoisting operation of the hoisting accessory.