Patents by Inventor Kazuo Hibi

Kazuo Hibi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5210844
    Abstract: An information processing apparatus having at least one processor and a main storage, accessed by the processor, and capable of providing a plurality of logical information processing apparatus by logically partitioning the information processing apparatus. The information processing apparatus includes a main storage partitioned into a plurality of memory areas, each of the memory areas corresponding to one of the plurality of logical information processing apparatus. The information processing apparatus further includes a first storage unit for storing identification information for each of the memory areas identifying the logical information processing apparatus allocated to each memory and a read unit for reading the identification information from the first storage unit when the main storage is to be accessed by one of the plurality of logical information processing apparatus. Each of the plurality of logical information processing apparatus possesses a unique identification information.
    Type: Grant
    Filed: September 26, 1989
    Date of Patent: May 11, 1993
    Assignees: Hitachi, Ltd., Hitachi Computer Engineering Co., Ltd.
    Inventors: Nobuyuki Shimura, Kazuo Hibi, Yoshio Oshima
  • Patent number: 4326248
    Abstract: A multiple virtual storage control system for a data processing system for handling a plurality of virtual spaces is disclosed. Virtual addresses indicative of addresses in the virtual spaces are translated to real addresses by a translation table. When a new virtual space is established by setting a first address or segment table origin address (STO address) of the translation table, a virtual space number is assigned to the established virtual space by an STO address stack, which comprises a definite number of registers. The number of virtual space numbers assigned is larger than the number of registers. The virtual addresses and the corresponding real addresses are stored in a high-speed address translator so that the virtual addresses are translated to the real addresses at a high speed. When an overflow of the virtual space number assigned in the STO address stack takes place, the plurality of virtual spaces registered in the high-speed address translator are simultaneously purged.
    Type: Grant
    Filed: February 22, 1979
    Date of Patent: April 20, 1982
    Assignee: Hitachi, Ltd.
    Inventors: Mamoru Hinai, Chikahiko Izumi, Kazuo Hibi