Abstract: An arithmetic processing device includes: an arithmetic unit configured to execute an arithmetic operation; and a stream engine configured to execute stream processing, wherein a data bus of the arithmetic unit and a data bus of the stream engine are tightly coupled with each other.

Abstract: A product-sum operation circuit that performs a matrix product of a first-matrix and a second-matrix to output a third-matrix, includes; a plurality of multipliers; a plurality of first-adders each of which is configured to add two multiplication results of the plurality of multipliers; a plurality of second-adders each of which is configured to add two addition results of the plurality of the first-adders; an input selector configured to output an element of the first-matrix and an element of the second-matrix to input terminals of the plurality of multipliers according to the number of rows and the number of columns of the first-matrix and the second-matrix; and an output selector configured to select and output the addition results of each of the plurality of first-adders or each of the plurality of second-adders according to the number of rows and the number of columns of the first-matrix and the second-matrix, as the third-matrix.

Abstract: A matrix calculation unit may include a matrix operation unit and a converting unit. The matrix operation unit may include functions to perform a matrix operation of a first size with respect to data stored in a memory, and to perform a matrix operation of a second size with respect to the data stored in the memory, where the second size is enlarged from the first size. The converting unit may convert in at least one direction in the memory between a data array suited for the matrix operation of the first size and a data array suited for the matrix operation of the second size.

Abstract: An data supply circuit includes a buffer configured to store a plurality of data items each having a first width, a memory access unit configured to read source data stored in memory and to store the source data as one or more data items each having the first width in the buffer, and a selection control unit configured to repeat multiple times an operation of reading a data item having a second width shorter than or equal to the first width to read a plurality of data items each having the second width contiguously and sequentially from the buffer and configured to continue to read from a head end of the source data upon a read portion reaching a tail end of the source data.

Abstract: A product-sum operation circuit that performs a matrix product of a first-matrix and a second-matrix to output a third-matrix, includes; a plurality of multipliers; a plurality of first-adders each of which is configured to add two multiplication results of the plurality of multipliers; a plurality of second-adders each of which is configured to add two addition results of the plurality of the first-adders; an input selector configured to output an element of the first-matrix and an element of the second-matrix to input terminals of the plurality of multipliers according to the number of rows and the number of columns of the first-matrix and the second-matrix; and an output selector configured to select and output the addition results of each of the plurality of first-adders or each of the plurality of second-adders according to the number of rows and the number of columns of the first-matrix and the second-matrix, as the third-matrix.

Abstract: An arithmetic processing device includes: an arithmetic unit configured to execute an arithmetic operation; and a stream engine configured to execute stream processing, wherein a data bus of the arithmetic unit and a data bus of the stream engine are tightly coupled with each other.

Abstract: A data processing device has: a shift circuit that makes data with a certain bit length to be input therein for each cycle, and shifts the data to delete first invalid data in the data; and a gate circuit that cuts, when data as a result of combining pieces of the shifted data for each cycle has the certain bit length or more, first data with the certain bit length to output the data to an outside.

Abstract: A matrix calculation unit may include a matrix operation unit and a converting unit. The matrix operation unit may include functions to perform a matrix operation of a first size with respect to data stored in a memory, and to perform a matrix operation of a second size with respect to the data stored in the memory, where the second size is enlarged from the first size. The converting unit may convert in at least one direction in the memory between a data array suited for the matrix operation of the first size and a data array suited for the matrix operation of the second size.

Abstract: An arithmetic processing unit that performs processing of a stream-type includes an arithmetic unit configured to operate an input operand to obtain a result of operation; and a data input and output unit configured to read the input operand out of a memory when an instruction which is issued in a case where a stream length of the input operand is shorter than a stream length of an output operand corresponding to the input operand and includes data indicating a recursive rule used when the input operand is read out, to supply the read input operand, and to store the result of the operation obtained by the arithmetic unit in the memory as the output operand, wherein the arithmetic unit 20 operates the input operand read out by the data input and output unit and outputs the result of operation to the data input and output unit.