Patents by Inventor Kazuo Kawamura
Kazuo Kawamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8679973Abstract: The method of manufacturing the semiconductor device comprises forming a transistor including a gate electrode and a source/drain diffused layer over a semiconductor substrate, forming a nickel platinum film over the semiconductor substrate, covering the gate electrode and the source/drain diffused layer, making a first thermal processing to react the nickel platinum film with the source/drain diffused layer to form a nickel platinum silicide film, and removing an unreacted part of the nickel platinum film using a chemical liquid of 71° C. or more containing hydrogen peroxide.Type: GrantFiled: October 11, 2007Date of Patent: March 25, 2014Assignee: Fujitsu Semiconductor LimitedInventors: Shinichi Akiyama, Kazuo Kawamura, Masanori Uchida
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Patent number: 8536708Abstract: A method of manufacturing a semiconductor device has forming, in a dielectric film, a first opening and a second opening located in the first opening, forming a first metal film containing a first metal over a whole surface, etching the first metal film at a bottom of the second opening using a sputtering process and forming a second metal film containing a second metal over the whole surface, and burying a conductive material in the second opening and the first opening.Type: GrantFiled: September 6, 2012Date of Patent: September 17, 2013Assignee: Fujitsu Semiconductor LimitedInventors: Shinichi Akiyama, Kazuo Kawamura, Hisaya Sakai, Hirofumi Watatani, Kazuya Okubo
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Publication number: 20120326315Abstract: A method of manufacturing a semiconductor device has forming, in a dielectric film, a first opening and a second opening located in the first opening, forming a first metal film containing a first metal over a whole surface, etching the first metal film at a bottom of the second opening using a sputtering process and forming a second metal film containing a second metal over the whole surface, and burying a conductive material in the second opening and the first opening.Type: ApplicationFiled: September 6, 2012Publication date: December 27, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Shinichi Akiyama, Kazuo Kawamura, Hisaya Sakai, Hirofumi Watatani, Kazuya Okubo
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Patent number: 8338953Abstract: A method of manufacturing a semiconductor device has forming, in a dielectric film, a first opening and a second opening located in the first opening, forming a first metal film containing a first metal over a whole surface, etching the first metal film at a bottom of the second opening using a sputtering process and forming a second metal film containing a second metal over the whole surface, and burying a conductive material in the second opening and the first opening.Type: GrantFiled: June 20, 2011Date of Patent: December 25, 2012Assignee: Fujitsu Semiconductor LimitedInventors: Shinichi Akiyama, Kazuo Kawamura, Hisaya Sakai, Hirofumi Watatani, Kazuya Okubo
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Publication number: 20120171864Abstract: The method of manufacturing the semiconductor device comprises the steps of forming a MOS transistor 26 including a gate electrode 16 and source/drain diffused layers 24 formed in the silicon substrate 10 on both sides of the gate electrode 16, forming a NiPt film 28 over the silicon substrate 10, covering the gate electrode 16 and the source/drain diffused layers 26, making thermal processing to react the NiPt film 28 with the upper parts of the source/drain diffused layers 24 to form Ni(Pt)Si films 34a, 34b on the source/drain diffused layers 24, and removing selectively the unreacted part of the NiPt film 28 using a chemical liquid of above 71° C. including 71° C. containing hydrogen peroxide and forming an oxide film on the surface of the Ni(Pt)Si films 34a, 34b.Type: ApplicationFiled: March 14, 2012Publication date: July 5, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Shinichi AKIYAMA, Kazuo KAWAMURA, Masanori UCHIDA
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Patent number: 8076239Abstract: A method of manufacturing a semiconductor device, includes the steps of forming an insulating film on a semiconductor substrate having a silicide layer, forming a hole in the insulating film on the silicide layer, cleaning an inside of the hole and a surface of the silicide layer, forming a titanium layer on a bottom surface and an inner peripheral surface of the hole by a CVD method, forming a copper diffusion preventing barrier metal layer on the titanium layer in the hole, and burying a copper layer in the hole.Type: GrantFiled: February 15, 2008Date of Patent: December 13, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Kazuo Kawamura, Shinichi Akiyama, Satoshi Takesako
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Publication number: 20110241211Abstract: A method of manufacturing a semiconductor device has forming, in a dielectric film, a first opening and a second opening located in the first opening, forming a first metal film containing a first metal over a whole surface, etching the first metal film at a bottom of the second opening using a sputtering process and forming a second metal film containing a second metal over the whole surface, and burying a conductive material in the second opening and the first opening.Type: ApplicationFiled: June 20, 2011Publication date: October 6, 2011Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Shinichi AKIYAMA, Kazuo KAWAMURA, Hisaya SAKAI, Hirofumi WATATANI, Kazuya OKUBO
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Patent number: 8030207Abstract: A method of manufacturing a semiconductor device has forming, in a dielectric film, a first opening and a second opening located in the first opening, forming a first metal film containing a first metal over a whole surface, etching the first metal film at a bottom of the second opening using a sputtering process and forming a second metal film containing a second metal over the whole surface, and burying a conductive material in the second opening and the first opening.Type: GrantFiled: April 28, 2008Date of Patent: October 4, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Shinichi Akiyama, Kazuo Kawamura, Hisaya Sakai, Hirofumi Watatani, Kazuya Okubo
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Patent number: 7977194Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first MISFET including first source/drain regions and a first gate electrode of a polycrystalline silicon, and a second MISFET including second source/drain regions and a second gate electrode of a polycrystalline silicon and having a gate length larger than that of the first gate electrode; and substituting the polycrystalline silicon forming the first and the second gate electrodes with a metal silicide. In the step of substituting the polycrystalline silicon with the metal silicide, the polycrystalline silicon forming the first gate electrode is totally substituted with the metal silicide and a part of polycrystalline silicon forming the second gate electrode is substituted with the metal silicide by utilizing that the gate length of the second gate electrode is larger than the gate length of the first gate electrode.Type: GrantFiled: July 25, 2006Date of Patent: July 12, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Hidenobu Fukutome, Hiroyuki Ohta, Kazuo Kawamura, Kimihiko Hosaka
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Patent number: 7829461Abstract: A semiconductor device fabrication method by which the thermal stability of nickel silicide can be improved. Nickel (or a nickel alloy) is formed over a semiconductor substrate on which a gate region, a source region, and a drain region are formed. Dinickel silicide is formed by performing a first annealing step, followed by a selective etching step. By performing a plasma treatment step, plasma which contains hydrogen ions is generated and the hydrogen ions are implanted in the dinickel silicide or the gate region, the source region, and the drain region under the dinickel silicide. The dinickel silicide is phase-transformed into nickel silicide by performing a second annealing step.Type: GrantFiled: September 12, 2007Date of Patent: November 9, 2010Assignee: Fujitsu Semiconductor LimitedInventors: Kazuo Kawamura, Shinichi Akiyama
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Publication number: 20100165179Abstract: An imaging method for taking an image using an imaging apparatus including an imaging device which includes first rows of pixels including first groups of light receiving elements and second rows of pixels including second groups of light receiving elements; first charge transfer lines; and second charge transfer lines, includes steps of: consecutively performing a subject-illuminating imaging and a subject-non-illuminating imaging, responsive to an input of an imaging instruction; reading out the charges accumulated in the first groups and the second groups of light receiving elements, and transferring the charges via the first and second charge transfer lines, respectively, after the subject-illuminating imaging and the subject-non-illuminating imaging; and acquiring an image by the subject-illuminating imaging and an image by the subject-non-illuminating imaging from the charges having been read out and transferred from the first groups and the second groups of light receiving elements, respectively.Type: ApplicationFiled: December 23, 2009Publication date: July 1, 2010Applicant: FUJIFILM CorporationInventor: Kazuo KAWAMURA
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Patent number: 7649232Abstract: A p-channel MOS transistor includes source and drain regions of p-type formed in a silicon substrate at respective lateral sides of a gate electrode wherein each of the source and drain regions of p-type includes any of a metal film region and a metal compound film region as a compressive stress source accumulating therein a compressive stress.Type: GrantFiled: July 25, 2005Date of Patent: January 19, 2010Assignee: Fujitsu Microelectronics LimitedInventors: Naoyoshi Tamura, Kazuo Kawamura, Akira Katakami
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Patent number: 7557446Abstract: A semiconductor device formed by the steps of forming a contact hole in an insulation film so as to extend therethrough and so as to expose a conductor body at a bottom part of the contact hole, forming a barrier metal film of tungsten nitride on the bottom part and a sidewall surface of the contact hole with a conformal shape to the bottom part and the sidewall surface of the contact hole, forming a tungsten layer so as to fill the contact hole via the barrier metal film, and forming a tungsten plug in the contact hole by the tungsten layer by polishing away a part of the tungsten film on the insulation film until a surface of the insulation film is exposed, wherein there is conducted a step of cleaning a surface of the conductor body prior to the forming step of the barrier metal film.Type: GrantFiled: June 30, 2008Date of Patent: July 7, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Takeshi Ito, Satoshi Inagaki, Yasunori Uchino, Kazuo Kawamura
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Publication number: 20090075477Abstract: According to an aspect of an embodiment, a method of manufacturing a semiconductor device has forming a silicon-containing layer over a semiconductor substrate, forming a metal layer over the semiconductor substrate and the silicon-containing layer, forming a silicide-containing layer over the semiconductor substrate and the silicon-containing layer by heat treatment of the semiconductor substrate and the silicon-containing layer, and applying flash annealing to the silicide-containing layer.Type: ApplicationFiled: September 10, 2008Publication date: March 19, 2009Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Kazuo KAWAMURA, Shinichi AKIYAMA, Kazuya OKUBO, Akira KATAKAMI, Naoki IDANI, Takashi WATANABE
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Publication number: 20090032844Abstract: A method of manufacturing a semiconductor device has forming a transistor including a source and a drain, forming a mixed crystal layer over the source and the drain, forming a silicide layer over the mixed crystal layer, forming a first insulating film and a second insulating film over the silicide layer, forming a contact hole, performing an oxygen plasma treatment, and forming a conductive plug in the contact hole.Type: ApplicationFiled: July 29, 2008Publication date: February 5, 2009Applicants: FUJITSU LIMITED, FUJITSU MICROELECTRONICS LIMITEDInventors: Jusuke OGURA, Hikaru KOKURA, Hiroshi MORIOKA, Kazuo KAWAMURA
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Publication number: 20080303171Abstract: A semiconductor device formed by the steps of forming a contact hole in an insulation film so as to extend therethrough and so as to expose a conductor body at a bottom part of the contact hole, forming a barrier metal film of tungsten nitride on the bottom part and a sidewall surface of the contact hole with a conformal shape to the bottom part and the sidewall surface of the contact hole, forming a tungsten layer so as to fill the contact hole via the barrier metal film, and forming a tungsten plug in the contact hole by the tungsten layer by polishing away a part of the tungsten film on the insulation film until a surface of the insulation film is exposed, wherein there is conducted a step of cleaning a surface of the conductor body prior to the forming step of the barrier metal film.Type: ApplicationFiled: June 30, 2008Publication date: December 11, 2008Applicant: FUJITSU LIMITEDInventors: Takeshi Ito, Satoshi Inagaki, Yasunori Uchino, Kazuo Kawamura
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Publication number: 20080284027Abstract: A method of manufacturing a semiconductor device has forming, in a dielectric film, a first opening and a second opening located in the first opening, forming a first metal film containing a first metal over a whole surface, etching the first metal film at a bottom of the second opening using a sputtering process and forming a second metal film containing a second metal over the whole surface, and burying a conductive material in the second opening and the first opening.Type: ApplicationFiled: April 28, 2008Publication date: November 20, 2008Applicant: FUJITSU LIMITEDInventors: Shinichi AKIYAMA, Kazuo KAWAMURA, Hisaya SAKAI, Hirofumi WATATANI, Kazuya OKUBO
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Publication number: 20080265417Abstract: A method of manufacturing a semiconductor device, includes the steps of forming an insulating film on a semiconductor substrate having a silicide layer, forming a hole in the insulating film on the silicide layer, cleaning an inside of the hole and a surface of the silicide layer, forming a titanium layer on a bottom surface and an inner peripheral surface of the hole by a CVD method, forming a copper diffusion preventing barrier metal layer on the titanium layer in the hole, and burying a copper layer in the hole.Type: ApplicationFiled: February 15, 2008Publication date: October 30, 2008Applicant: FUJITSU LIMITEDInventors: Kazuo KAWAMURA, Shinichi Akiyama, Satoshi Takesako
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Patent number: 7432180Abstract: A method of fabricating a semiconductor device comprises the step of forming a nickel monosilicide layer selectively over a silicon region defined by an insulation film by a self-aligned process. The self-aligned process comprises the steps of forming a metallic nickel film on a silicon substrate on which the insulation film and the silicon region are formed, such that the metallic nickel film covers the insulation film and the silicon region, forming a first nickel silicide layer primarily of a Ni2Si phase on a surface of the silicon region of the metallic nickel film by applying an annealing process to the silicon substrate, removing the metallic nickel film, after the step of forming the first nickel silicide layer, by a selective wet etching process, and converting the first nickel silicide layer to a second nickel silicide layer primarily of a NiSi phase by a thermal annealing process conducted in a silane gas.Type: GrantFiled: May 16, 2006Date of Patent: October 7, 2008Assignee: Fujitsu LimitedInventors: Yasunori Uchino, Kazuo Kawamura, Naoyoshi Tamura
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Patent number: 7429525Abstract: A method of fabricating a semiconductor device includes the steps of forming a metallic nickel film on a silicon substrate such that the metallic nickel film covers an insulation film on the silicon substrate and a silicon surface of the silicon substrate, annealing the silicon substrate in a silane gas ambient at a temperature not exceeding 220° C. to form a first nickel silicide layer having a composition primarily of Ni2Si on the silicon surface and a surface of the metallic nickel film, removing the metallic nickel film after the step of forming the nickel silicide layer by a wet etching process, and converting the first nickel silicide layer to a second nickel silicide layer primarily of nickel monosilicide (NiSi) by applying a thermal annealing process.Type: GrantFiled: May 16, 2006Date of Patent: September 30, 2008Assignee: Fujitsu LimitedInventors: Yasunori Uchino, Kazuo Kawamura, Naoyoshi Tamura