Patents by Inventor Kazuo Matsuno

Kazuo Matsuno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4025902
    Abstract: A general purpose sequence controller wherein a schematic electric circuit diagram comprising a ladder network of circuit lines disposed between two vertical bus lines is changeable and simulated by a special purpose control program. A logic operation circuit comprises first and second circuit means for examining an external input signal in accordance with examine commands of logical AND and OR functions, respectively, first and second memory means for temporarily memorizing the examined results of the first and second circuit means, respectively, third memory means for temporarily memorizing the application of the examine command of the logical OR function, and identifying circuit means for identifying the examined results of the logic operations in accordance with the contents of the first, second and third memory means.
    Type: Grant
    Filed: June 13, 1974
    Date of Patent: May 24, 1977
    Assignee: Toyoda Koki Kabushiki Kaisha
    Inventors: Hisaji Nakao, Katutoshi Naruse, Kazuhiko Hasegawa, Sadao Kawade, Yasufumi Tokura, Kazuo Matsuno
  • Patent number: 4019175
    Abstract: A programmable sequence controller is disclosed which includes a controller memory having at least one read-only memory unit for storing a sequence program comprising a series of instructions each including an operation code and address information. An operation control device is also provided for examining an external input in accordance with an appropriate instruction. An input network permits application of external inputs designated by the address information to the operation control device, and an output network is provided for transmitting a control signal based on the examination result from the operation control device. A program input network including a read-write memory is provided for storing a part of the sequence program, which part is loadable in one read-only memory unit.
    Type: Grant
    Filed: April 15, 1975
    Date of Patent: April 19, 1977
    Assignees: Toyoda Koki Kabushiki Kaisha, Toyota Jidosha Kogyo Kabushiki Kaisha
    Inventors: Hisaji Nakao, Yasufumi Tokura, Kazuo Matsuno, Toshihiko Yomogida