Abstract: In a system comprising a memory, an input/output control device, a direct memory access controller and a data bus, the transfer of data between the memory and the input/output control device via the data bus by means of said direct memory access controller during the period of direct memory access mode is effected by controlling the data transfer direction on a data bus so that a control signal for determining the direction of transferring the data by said data bus is recognized in an inverted manner at the memory or the input/output control device only during the period of a data transfer cycle in the direct memory access mode.

Abstract: A counter particularly useful for a program counter comprising a plurality of logic units representative of digits of information data being stored in the counter, each logic unit including a flip-flop circuit indicative of the value of each digit, an exclusive OR circuit connected with the input of the flip-flop circuit and an OR circuit connected with an input of the exclusive OR circuit, the output of the flip-flop circuit being connected to another input of the exclusive OR circuit. A control signal and a carry signal are supplied to the inputs of the OR circuit of an associated one logic unit. The least significant digit logic unit lacks an OR circuit since no carry signal is supplied thereto so that a least significant digit control signal is directly supplied to one input of the exclusive OR circuit of the least significant digit logic unit.