Patents by Inventor Kazuo Mitsui

Kazuo Mitsui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7238992
    Abstract: In a semiconductor integrated circuit for a DC—DC converter, an nMOS-type transistor Qn of a CMOS inverter 1c constituting a driver 1 is electrically floated from a substrate 12 through an n-type well region 11. Thus, the nMOS-type transistor Qn is electrically insulated from other transistors such as an npn-type transistor Q1 and an L-pnp-type transistor Q2 constituting a feedback control system 9 through the n-type well region 11. Stable operation is performed with a minute current without producing a malfunction caused by the influence of a parasitic current, even if the drain potential of an nMOS-type transistor is reduced to the ground potential or lower at the time of switching by a driver constituted from a CMOS inverter, to facilitate lower power consumption and higher efficiency, and also to eliminate a constraint on layout design of components.
    Type: Grant
    Filed: January 14, 2005
    Date of Patent: July 3, 2007
    Assignee: NEC Electronics Corporation
    Inventors: Yuri Komori, Kazuo Mitsui
  • Publication number: 20050151525
    Abstract: In a semiconductor integrated circuit for a DC-DC converter, an nMOS-type transistor Qn of a CMOS inverter 1c constituting a driver 1 is electrically floated from a substrate 12 through an n-type well region 11. Thus, the nMOS-type transistor Qn is electrically insulated from other transistors such as an npn-type transistor Q1 and an L-pnp-type transistor Q2 constituting a feedback control system 9 through the n-type well region 11. Stable operation is performed with a minute current without producing a malfunction caused by the influence of a parasitic current, even if the drain potential of an nMOS-type transistor is reduced to the ground potential or lower at the time of switching by a driver constituted from a CMOS inverter, to facilitate lower power consumption and higher efficiency, and also to eliminate a constraint on layout design of components.
    Type: Application
    Filed: January 14, 2005
    Publication date: July 14, 2005
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Yuri Komori, Kazuo Mitsui
  • Patent number: 6885905
    Abstract: An electric-circuit fabricating system for fabricating an electric circuit, by performing a working operation on a circuit substrate, including a substrate holding device to hold the substrate, an imaging device to image a surface of the substrate on which the working operation is to be performed, an imaging control device to control the imaging device to take an image of a substrate-position fiducial mark provided on the substrate, and obtaining substrate-position information on the basis of the image, and a working device to perform the working operation on the substrate, on the basis of the substrate-position information, and wherein the imaging control device is operable to control the imaging device to take an image of a substrate ID mark provided on the substrate as held by the substrate holding device, for obtaining substrate identifying information identifying the substrate, on the basis of the image of the substrate ID mark.
    Type: Grant
    Filed: September 18, 2002
    Date of Patent: April 26, 2005
    Assignee: Fuji Machine Mfg. Co., Ltd.
    Inventors: Seigo Kodama, Takayoshi Kawai, Kazuo Mitsui
  • Patent number: 6861269
    Abstract: A method of fabricating an electric circuit, including first and second working processes of performing respective first and second working operations on a circuit substrate, where3in the first working process includes a first substrate-identifying step of obtaining substrate identifying information identifying the substrate on which the first working operation is to be performed, a specific-information obtaining step of recognizing a specific-information providing portion of the substrate, to obtain specific information indicating at least one specific characteristic of the substrate, a first working step of performing the first working operation on the basis of the obtained specific information, and a specific-information storing step of storing the specific information in relation to the substrate identifying information, and the second working process includes a second substrate-identifying step of obtaining the substrate identifying information identifying the substrate on which the second working operat
    Type: Grant
    Filed: September 18, 2002
    Date of Patent: March 1, 2005
    Assignee: Fuji Machine Mfg. Co., Ltd.
    Inventors: Takayoshi Kawai, Kazuo Mitsui, Seigo Kodama
  • Patent number: 6850855
    Abstract: Where a result of operations to mount electronic components is inspected, for example, an operating procedure of an inspecting operation is determined on the basis of mounting-condition information such as used-device information relating to used suction nozzles, feeders and other devices, and mounting-result information such as information relating to recovery actions. The operating procedure may be determined on the basis of device-usage historical information as well. For instance, the inspection operation is performed on inspecting objects selected from the mounting objects, such as mounting objects mounted with nozzles of high mounting defect ratios, mounting objects mounted with feeders of long use, etc. Additional inspecting objects are selected such that the inspection can be effected within a predetermined time. The inspecting order may be determined so as to complete the inspection in a shortest possible time.
    Type: Grant
    Filed: October 7, 2002
    Date of Patent: February 1, 2005
    Assignee: Fuji Machine Manufacturing Company, Limited
    Inventors: Takayoshi Kawai, Kazuo Mitsui
  • Publication number: 20040249689
    Abstract: An enterprise resource planning application system provided in the form of a plurality of business packages supports a backbone executed by a computer system in an integrated manner. The enterprise resource planning application system extracts from a plurality of standard functions provided by the business packages standard functions that realize a business process common to different types of business, and executes the business process only by a combination of the standard functions extracted.
    Type: Application
    Filed: April 2, 2004
    Publication date: December 9, 2004
    Inventors: Hitoshi Naraki, Kazuo Mitsui
  • Publication number: 20030125895
    Abstract: Where a result of operations to mount electronic components is inspected, for example, an operating procedure of an inspecting operation is determined on the basis of mounting-condition information such as used-device information relating to used suction nozzles, feeders and other devices, and mounting-result information such as information relating to recovery actions. The operating procedure may be determined on the basis of device-usage hysteresis information as well. For instance, the inspection operation is performed on inspecting objects selected from the mounting objects, such as mounting objects mounted with nozzles of high mounting defect ratios, mounting objects mounted with feeders of long use, etc. Additional inspecting objects are selected such that each mounting object is inspected at a predetermined frequency or such that the inspection can be effected within a predetermined time. The inspecting order may be determined so as to complete the inspection in a shortest possible time.
    Type: Application
    Filed: October 7, 2002
    Publication date: July 3, 2003
    Applicant: FUJI MACHINE MFG. CO., LTD.
    Inventors: Takayoshi Kawai, Kazuo Mitsui
  • Publication number: 20030059961
    Abstract: An electric-circuit fabricating system for fabricating an electric circuit, by performing a working operation on a circuit substrate, including a substrate holding device to hold the substrate, an imaging device to image a surface of the substrate on which the working operation is to be performed, an imaging control device to control the imaging device to take an image of a substrate-position fiducial mark provided on the substrate, and obtaining substrate-position information on the basis of the image, and a working device to perform the working operation on the substrate, on the basis of the substrate-position information, and wherein the imaging control device is operable to control the imaging device to take an image of a substrate ID mark provided on the substrate as held by the substrate holding device, for obtaining substrate identifying information identifying the substrate, on the basis of the image of the substrate ID mark.
    Type: Application
    Filed: September 18, 2002
    Publication date: March 27, 2003
    Applicant: Fuji Machine Mfg. Co., Ltd.
    Inventors: Seigo Kodama, Takayoshi Kawai, Kazuo Mitsui
  • Publication number: 20030059964
    Abstract: A method of fabricating an electric circuit, including first and second working processes of performing respective first and second working operations on a circuit substrate, wherein the first working process includes a first substrate-identifying step of obtaining substrate identifying information identifying the substrate on which the first working operation is to be performed, a specific-information obtaining step of recognizing a specific-information providing portion of the substrate, to obtain specific information indicating at least one specific characteristic of the substrate, a first working step of performing the first working operation on the basis of the obtained specific information, and a specific-information storing step of storing the specific information in relation to the substrate identifying information, and the second working process includes a second substrate-identifying step of obtaining the substrate identifying information identifying the substrate on which the second working operati
    Type: Application
    Filed: September 18, 2002
    Publication date: March 27, 2003
    Applicant: Fuji Machine Mfg. Co., Ltd.
    Inventors: Takayoshi Kawai, Kazuo Mitsui, Seigo Kodama
  • Patent number: 5333081
    Abstract: A magnetic head driving circuit is provided which has first and second transistors having the bases respectively connected to first and second input terminals and the collectors supplied with a power source voltage, third and fourth transistors having the collectors respectively connected to the emitters of the first and second transistors, and a magnetic head and surge absorbing resistor disposed in a parallel connection with each other between the emitters of the first and second transistors. Delay circuits are respectively disposed between the input terminal and the base of the fourth transistor and between the second input terminal and the base of the third transistor. If there has a time delay in inverting action generated between the first and second transistors, the reverse bias voltage acting between the base and emitter of the first and/or second transistor will be impossible to be increased, so that the switching time of the magnetic head current can be shortened.
    Type: Grant
    Filed: September 28, 1992
    Date of Patent: July 26, 1994
    Assignee: NEC Corporation
    Inventor: Kazuo Mitsui
  • Patent number: 5034684
    Abstract: A probe device having a loader unit and two measuring units is disclosed. Each of the loader and measuring units is an independent unit supported by an independent casing. Each of the loader and measuring units has its exclusive slave CPU and integrated circuit members are under the control of this slave CPU to manage operations of members at the unit. The slave CPUs are connected to a master CPU, which controls the slave CPUs and which is also an independent unit, and they are connected to one another only through the master CPU. Program language is common to the master and slave CPUs and the units can be electrically connected to form an integral control system in which signals are exchanged among the units.
    Type: Grant
    Filed: October 24, 1989
    Date of Patent: July 23, 1991
    Assignee: Tokyo Electron Limited
    Inventors: Kazuo Mitsui, Hiroshi Suzuki, Toshihiro Hosoda, Toshihiko Iijima, Shinji Niwa, Tetsuji Watanabe, Hideo Sakagawa, Tetsuo Sato
  • Patent number: 4926421
    Abstract: In a mobile radio telephone system having multiple base stations controlled by a single line control unit, all base stations use a single common control channel in addition to their voice channels to communicate with a mobile station. If a calling signal from a mobile station is received by two or more base stations at once on the common control channel, the base station with the highest received signal level is selected. If voice signal quality becomes degraded during a call, the call is handed off to the base station with the highest received signal level.
    Type: Grant
    Filed: October 18, 1988
    Date of Patent: May 15, 1990
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Minori Kawano, Kazuo Mitsui, Masaharu Hirooka, Yasushi Ozu, Nagayasu Harada, Nobuhiro Kimura
  • Patent number: 4915649
    Abstract: A connector comprises a housing provided with a recess (7), a terminal cavity (9) and a gap (10), and a contact piece (2) provided with a base portion (2') and bifurcated free ends (3, 3'). Contact terminals (6, 6') of wires (W, W'), project into the recess through the terminal cavity. The base portion of the contact piece is fitted into the gap, the bifurcated free ends of the contact piece project into the recess, and only one of the bifurcated free ends is normally in contact with one of the contact terminals. Therefore, when an arm of the housing of an other connector is fitted into the recess, the other of the bifurcated free ends is brought into contact with the other of the contact terminals and completes an electrical connection between them.
    Type: Grant
    Filed: July 20, 1988
    Date of Patent: April 10, 1990
    Assignee: Sumitomo Wiring Systems, Ltd.
    Inventors: Hiroyuki Shimazu, Kazuo Mitsui
  • Patent number: 4385795
    Abstract: A connector adapted to be detachably connected to a flat electric cable having terminal members including contact portions and legs connected to the contact portions which are bent in such a manner that the end portions of the legs are staggered alternately in a zigzag manner forming two lines of legs. The end portions of the legs extend either in the axial or the direction perpendicular to the axial direction of the connector. The legs may be made of equal length before bending and or bent preferably such that the ends of all of the legs flow substantially in the same plane.
    Type: Grant
    Filed: December 10, 1980
    Date of Patent: May 31, 1983
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Seiji Endoh, Shotaro Tada, Toru Kuga, Yasuo Takeda, Kazuo Mitsui, Yoji Yoshimura