Abstract: A semiconductor integrated circuit is constituted by a logic circuit, auxiliary logic circuits, and a selection circuit For example, the logic circuit contains unit inverters, and the auxiliary logic circuits are each correspondingly constituted by a pair of unit inverters. The selection circuit selectively activates the auxiliary logic circuit(s) relatively with the logic circuit in response to the period of the input clock signal (CLK2S), supplied to the logic circuit, which is not smaller than the prescribed shortest period (T1). Even though the average current flowing in the logic circuit decreases due to the relatively long period of the input clock signal, it is possible to compensate for the power deficiency by adequately activating the auxiliary logic circuit(s). Therefore, substantially no variation occurs in the junction temperature and jitter with respect to transistors contained in the logic circuit, regardless of variations of the input clock signal.

Abstract: A D-FF circuit comprises: a master flip-flop and a slave flip-flop which operate in accordance with a plurality of clock signals generated by a clock signal generating circuit; wherein the slave flip-flop comprises: a clocked inverter which is disposed on a first stage of the slave flip-flop and which operates in accordance with at least one of the plurality of clock signals generated by the clock signal generating circuit, and a two-stage inverter which is connected in series with an output terminal of the clocked inverter.

Abstract: An inverter circuit suitable for use in a highly accurate measuring device such as an LSI tester provides a D flip-flop in addition to unit inverters and switching circuits, each of which contains a pair of a PMOS transistor and an NMOS transistor. The switching circuits are arranged in relation to the unit inverters that are connected together in a cascade connection manner. A clock signal (CLK1) consisting of clock pulses having a variable frequency is input to the unit inverter, while another clock signal (CLK3) having a constant frequency is input to the D flip-flop to produce a prescribed clock signal (CLK2, CLK4), which is continuously supplied to the switching circuits even when no clock pulse is input to the unit inverter. Thus, it is possible to avoid unwanted variations of junction temperature and response time (e.g., jitter).

Abstract: A D-FF circuit for operating a master flip-flop and a slave flip-flop at each predetermined timing in accordance with a plurality of clock signals generated by a clock signal generating circuit, wherein the clock signal generating circuit generates the plurality of clock signals at different timings, the slave flip-flop starts operating in accordance with a clock signal which is generated at an earlier timing than another clock signal generated by the clock signal generating circuit, and the master flip-flop stops operating in accordance with a clock signal which is generated at a later timing than another clock signal generated by the clock signal generating circuit.

Abstract: A logic product circuit having a plurality of transistors arranged in a matrix; a plurality of input terminals; and a single output terminal. The transistors in each column are connected in a line, forming a transistor array, the transistor arrays are connected in parallel between the output terminal and the ground, each of the input terminals is connected to the inputs to the transistors in all the columns, and the transistors to which each input terminal is connected are arranged in different rows.

Abstract: A D-FF circuit comprises: a master flip-flop and a slave flip-flop which operate in accordance with a plurality of clock signals generated by a clock signal generating circuit; wherein the slave flip-flop comprises: a clocked inverter which is disposed on a first stage of the slave flip-flop and which operates in accordance with at least one of the plurality of clock signals generated by the clock signal generating circuit, and a two-stage inverter which is connected in series with an output terminal of the clocked inverter.

Abstract: A D-FF circuit for operating a master flip-flop and a slave flip-flop at each predetermined timing in accordance with a plurality of clock signals generated by a clock signal generating circuit, wherein the clock signal generating circuit generates the plurality of clock signals at different timings, the slave flip-flop starts operating in accordance with a clock signal which is generated at an earlier timing than another clock signal generated by the clock signal generating circuit, and the master flip-flop stops operating in accordance with a clock signal which is generated at a later timing than another clock signal generated by the clock signal generating circuit.

Abstract: In a temperature stabilizing circuit, a reference temperature detecting means 11 converts the highest value of the junction temperature of and LSI 1 into a reference pulse number, and stores it. An operating temperature detecting means 12 converts the junction temperature of the LSI at the time of operation into an operating pulse number, and stores it. A current control means 13 subjects the operating pulse number and the reference pulse number to comparison, and increases or decreases an operating current flowing to a T. G. 10 so that the operation pulse number be equal to the reference pulse number, thereby to control the junction temperature. As a result, the jitter value of the timing generator made up of a CMOS gate array is greatly decreased.

Abstract: The present invention provides a semiconductor wafer tester including a substrate, at least one chip mounted on an upper surface of the substrate, the chip having function as a tester, the chip being electrically connected to a contact formed on a lower surface of the substrate through an internal wiring formed in the substrate, and a contact film having at least one first bump formed on an upper surface thereof and at least one second bump formed on a lower surface thereof, the first bump being electrically connected to the second bump through an internal wiring formed throughout the contact film, the contact film being to be disposed to be sandwiched between the substrate and a semiconductor wafer to be tested so that the first bump is in electrical contact with the contact of the substrate and the second bump is in electrical contact with the semiconductor wafer.

Abstract: A tester for integrated circuits, includes a testing set for supplying inputs for operating an integrated circuit to be tested and for measuring outputs of the integrated circuit to be tested, a semiconductor chip or wafer formed with at least some of the functions of the testing set, and a contact member through which the semiconductor chip or wafer is to come into electrical contact with the integrated circuit to be tested. Thus, it is not necessary to transmit test signals from the testing set, and hence it is possible to simplify the expensive hardware necessary for transmitting the test signals. As a result, the cost of the tester is markedly reduced.

Abstract: The apparatus for collectively burning-in or testing a plurality of semiconductor chips disposed on a wafer without dicing the chips into individuals, the apparatus including a testing substrate, an active circuit disposed on the testing substrate for activating chips disposed on the wafer to be tested, a plurality of pads disposed on the testing substrate and positioned so that the pads are disposed in alignment with bonding pads of the chips disposed on the wafer when the testing substrate is overlaid on the wafer, and an anisotropic conductive layer disposed on the pads.

Abstract: A memory circuit having a regular memory cell group, a redundant memory cell group, and an improved redundant decoder circuit for selecting the redundant memory cell group if there is any defect in the regular memory cell group. The redundant decoder circuit includes first and second programming circuits, and it is inoperative when the first programming circuit has not been programmed, operative when the first program element has been programmed and the second programming circuit has not been programmed, and inoperative when the second program circuit has been programmed.

Abstract: A compound semiconductor memory device having a redundancy configuration is disclosed. A fuse element to reject and replace a defective word line series is formed between a load transistor and a power voltage line in the primary decoder, and the word line is connected to the decoder without fuse element.

Abstract: For prompt response to an alternation of input signal, a latching circuit comprises two NAND gates each responsive to the input signal or the inverse thereof as well as an enable signal to produce an output signal or the inverse thereof, two level shifting circuits operative to shift the output signal and the inverse thereof in voltage level, and the controller providing a voltage level to partially define the shifting range of the output signal, and each of the level shifting circuits has a capacitor and two level shifters connected to the capacitor and the controller, respectively, so that the controller has no affection of the capacitor, thereby allowing the latching operation to be improved in speed.

Abstract: A static semiconductor memory device having an improved write circuit which can perform a write operation at a high speed is disclosed. The memory device comprises a plurality of memory cells each having a flip-flop holding a first level and a second level lower than the first level and a write circuit for operatively generating a write data signal which is applied to a selected one of the memory cells, the write data signal selectively assuming a low level of write data signal which is lower than the second level.

Abstract: A drive timing signal generator for generating a drive timing signal used for driving transfer gate transistors in a memory device, is disclosed. The generator includes a boost circuit for operative generating a boosted voltage above the power voltage and an additional boost circuit for further boosting the boosted voltage generated by the boost circuit after the generation of the boosted voltage in a write mode.

Abstract: A signal input circuit of a signal latch type includes a switch connected between a signal input terminal and a first node and first and second inverters connected in cascade between the first node and an output node, the output node being connected to the switch to control an ON/OFF state thereof. This circuit further includes a power-on reset circuit which detects the OFF state of the switch upon an application of a power voltage and changes the output node to a level that turns the switch ON.

Abstract: The semiconductor memory device includes an internal refresh circuit and an input circuit composed of first and second transistors of a different conductivity type having gates connected in common to an external control signal input terminal and connected in series with each other. A third transistor is connected in series to the first and second transistors. The third transistor is deactivated when the internal refresh circuit, operates to carry out a self-refresh mode, thereby suppressing a power consumption in the input circuit.

Abstract: A dynamic random access memory device is equipped with a test circuit for testing an internal refresh circuit. In a test mode, the content of an internal address counter is supplied to both the row of column address decoders, by which one memory cell disposed on the diagonal in a memory cell array is designated. Further, data is written into the designated memory cell from outside of the memory device, and the data stored in the designated memory cell is then read out to check whether the read-out signal is coincident with the written data.

Abstract: A buffer circuit, which supplies current to a capacitive load, has a first circuit for reducing the power supply charging current to the capacitive load during switching intervals. The first circuit includes a charge storage device precharged between inverter switching intervals to produce at least a portion of the load charging current during the switching intervals. A second circuit includes a switching element connected between the power supply and the capacitive load to electrically connect the power supply through the second circuit to the load at a selected time in the switching interval to supplement the charging current produced by the charge storage device.