Patents by Inventor Kazuo Nishiyama
Kazuo Nishiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11423496Abstract: To provide information useful to a variety of users engaged in real estate transactions. Provided is an information processing device including a graph rendering unit that renders a graph expressing an anticipated transaction price of a second real estate property, based on actual transaction prices and required transaction times of a first real estate property already bought or sold, and a display control unit that causes the graph to be displayed on a client device, wherein the graph includes an element expressing a probability distribution of the anticipated transaction price, and an element expressing an anticipated required transaction time corresponding to the anticipated transaction price.Type: GrantFiled: April 3, 2015Date of Patent: August 23, 2022Assignee: SONY CORPORATIONInventors: Shigeto Takenaka, Masanori Morishita, Kazuo Nishiyama, Yoshiyuki Nakamura, Hitomi Hoshi, Satsuki Eguchi, Hiroshi Takeda
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Publication number: 20170161852Abstract: To provide information useful to a variety of users engaged in real estate transactions. Provided is an information processing device including a graph rendering unit that renders a graph expressing an anticipated transaction price of a second real estate property, based on actual transaction prices and required transaction times of a first real estate property already bought or sold, and a display control unit that causes the graph to be displayed on a client device, wherein the graph includes an element expressing a probability distribution of the anticipated transaction price, and an element expressing an anticipated required transaction time corresponding to the anticipated transaction price.Type: ApplicationFiled: April 3, 2015Publication date: June 8, 2017Applicant: SONY CORPORATIONInventors: Shigeto TAKENAKA, Masanori MORISHITA, Kazuo NISHIYAMA, Yoshiyuki NAKAMURA, Hitomi HOSHI, Satsuki EGUCHI, Hiroshi TAKEDA
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Publication number: 20170140483Abstract: To provide information useful to a variety of users engaged in real estate transactions. Provided is an information processing device, including an appraisal value calculation unit that calculates an appraisal value of a real estate property by using a function which includes appraisal factors of the real estate property as variables and which is different depending on a location of the real estate property, an appropriate price calculation unit that calculates an appropriate price of the real estate property based on the appraisal value, an assessment creation unit that creates an assessment of the real estate property that includes the appropriate price, and a display control unit that causes the assessment to be displayed on a client device.Type: ApplicationFiled: April 3, 2015Publication date: May 18, 2017Inventors: SHIGETO TAKENAKA, MASANORI MORISHITA, KAZUO NISHIYAMA, HITOMI HOSHI, SATSUKI EGUCHI, YOSHIYUKI NAKAMURA, HIROSHI TAKEDA
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Publication number: 20140184915Abstract: An information processing device includes an operation input unit which inputs a user operation, a U/I screen generation unit which generates a U/I screen where a row of a plurality of category options for selecting a category and a row of a plurality of icons which is an option belonging to what is selected among the plurality of category options are orthogonally disposed, and when a selection of the option in the row of the plurality of category options is changed by the input user operation, an icon rotator which changes the plurality of icons from icons corresponding to those before a change of the category to icons corresponding to those after the change of the category by an animation display which causes the icon to rotate around the rotation axis in the same direction as a direction of the row of icons.Type: ApplicationFiled: December 12, 2013Publication date: July 3, 2014Applicant: SONY CORPORATIONInventors: MIYAKO TERASAWA, KAZUO NISHIYAMA, KOJI MATSUURA, KENICHI YAMAURA, KOU KUSANAGI, KEISUKE YANAGISAWA
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Patent number: 8224970Abstract: A Web-screen sharing system including a first and a second terminals, and a mediation server. The system includes: the terminals exchanging addresses through the mediation server; connecting the terminals using the addresses; when the first terminal is connected to any Web server, detecting whether a content in the Web server is security-protected; if protected, performing predetermined authentication processing with the Web server; when the authentication is successful, the Web server transmitting a content following the authentication processing to the first terminal; the first terminal displaying the content as a Web screen, and capturing the Web screen; transmitting an image file of the Web screen to the second terminal to display the screen on the second terminal, if not protected, the first terminal receiving the content from the Web server, and transmitting a URL at that time to the second terminal to display the Web screen.Type: GrantFiled: October 13, 2008Date of Patent: July 17, 2012Assignee: Sony CorporationInventor: Kazuo Nishiyama
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Publication number: 20100272251Abstract: Disclosed herein is an echo removing apparatus including: a sound input terminal configured to input an external sound signal from external equipment; a first echo removing device configured to, after admitting as input signals the external sound signal coming from the external equipment and input through the sound input terminal and a receiver sound signal transmitted from a calling party, estimate a first pseudo echo component from the external sound signal in order to remove the first pseudo echo component from the receiver sound signal; and a second echo removing device configured to, after admitting as input signals the external sound signal coming from the external equipment and input through the sound input terminal and a transmitter sound signal input from a microphone, estimate a second pseudo echo component from the external sound signal in order to remove the second pseudo echo component from the transmitter sound signal.Type: ApplicationFiled: March 31, 2010Publication date: October 28, 2010Applicant: Sony CorporationInventors: Tatsushi BANBA, Hiroshi Yamashita, Hidetoshi Ichioka, Kazuo Nishiyama, Shiro Omori, Kenji Suzuki, Shuichi Takizawa, Shinichi Sameshima
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Publication number: 20090119602Abstract: A Web-screen sharing system including a first and a second terminals, and a mediation server. The system includes: the terminals exchanging addresses through the mediation server; connecting the terminals using the addresses; when the first terminal is connected to any Web server, detecting whether a content in the Web server is security-protected; if protected, performing predetermined authentication processing with the Web server; when the authentication is successful, the Web server transmitting a content following the authentication processing to the first terminal; the first terminal displaying the content as a Web screen, and capturing the Web screen; transmitting an image file of the Web screen to the second terminal to display the screen on the second terminal, if not protected, the first terminal receiving the content from the Web server, and transmitting a URL at that time to the second terminal to display the Web screen.Type: ApplicationFiled: October 13, 2008Publication date: May 7, 2009Applicant: Sony CorporationInventor: Kazuo NISHIYAMA
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Patent number: 7471183Abstract: There is provided a joint structure of a wound iron core in which iron core characteristics can be enhanced by improving the distribution of magnetic flux within an iron core. A wound iron core is formed to provide a joining structure or a butt joining structure and a lap joining structure disposed in an appropriate arrangement in which the a margin of overlapping is more increased as being closer to an outer periphery from an inner periphery of the iron core, taking a distribution of magnetic flux density within the iron core into consideration.Type: GrantFiled: October 10, 2007Date of Patent: December 30, 2008Assignee: Hitachi Industrial Equipment Systems Co., Ltd.Inventors: Kouji Yamashita, Youji Matsuda, Kazuo Nishiyama, Masao Hosokawa, Kazuyuki Fukui, Hidemasa Yamaguchi, Tooru Honma, Hiroyuki Endou, Makoto Shinohara
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Publication number: 20080036565Abstract: There is provided a joint structure of a wound iron core in which iron core characteristics can be enhanced by improving the distribution of magnetic flux within an iron core. A wound iron core is formed to provide a joining structure or a butt joining structure and a lap joining structure disposed in an appropriate arrangement in which the a margin of overlapping is more increased as being closer to an outer periphery from an inner periphery of the iron core, taking a distribution of magnetic flux density within the iron core into consideration.Type: ApplicationFiled: October 10, 2007Publication date: February 14, 2008Applicant: Hitachi Industrial Equipment Systems Co., Ltd.Inventors: Kouji Yamashita, Youji Matsuda, Kazuo Nishiyama, Masao Hosokawa, Kazuyuki Fukui, Hidemasa Yamaguchi, Tooru Honma, Hiroyuki Endou, Makoto Shinohara
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Patent number: 7292127Abstract: There is provided a joint structure of a wound iron core in which iron core characteristics can be enhanced by improving the distribution of magnetic flux within an iron core. A wound iron core is formed to provide a joining structure or a butt joining structure and a lap joining structure disposed in an appropriate arrangement in which the a margin of overlapping is more increased as being closer to an outer periphery from an inner periphery of the iron core, taking a distribution of magnetic flux density within the iron core into consideration.Type: GrantFiled: May 25, 2005Date of Patent: November 6, 2007Assignee: Hitachi Industrial Equipment Systems Co., Ltd.Inventors: Kouji Yamashita, Youji Matsuda, Kazuo Nishiyama, Masao Hosokawa, Kazuyuki Fukui, Hidemasu Yamaguchi, Tooru Honma, Hiroyuki Endou, Makoto Shinohara
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Publication number: 20050280491Abstract: There is provided a joint structure of a wound iron core in which iron core characteristics can be enhanced by improving the distribution of magnetic flux within an iron core. A wound iron core is formed to provide a joining structure or a butt joining structure and a lap joining structure disposed in an appropriate arrangement in which the a margin of overlapping is more increased as being closer to an outer periphery from an inner periphery of the iron core, taking a distribution of magnetic flux density within the iron core into consideration.Type: ApplicationFiled: May 25, 2005Publication date: December 22, 2005Applicant: Hitachi, Ltd.Inventors: Kouji Yamashita, Youji Matsuda, Kazuo Nishiyama, Masao Hosokawa, Kazuyuki Fukui, Hidemasa Yamaguchi, Tooru Honma, Hiroyuki Endou, Makoto Shinohara
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Patent number: 6936525Abstract: A method of manufacturing the semiconductor chips comprises the steps of: pasting on a substrate an adhesive sheet having a property to retain its adhesive strength prior to a processing, then lose its adhesive strength after the processing; fixing a plurality of non-defective bare chips on this adhesive sheet, with their Al electrode pad surfaces facing down; coating a resin on a whole area other than the Al electrode pad surfaces of the plurality of non-defective bare chips including interspaces therebetween; applying a predetermined process to the adhesive sheet to weaken its adhesive strength of the adhesive sheet; peeling off a pseudo wafer bonding non-defective bare chips; and dicing the plurality of non-defective bare chips into a discrete non-defective electronic part by cutting the pseudo wafer at a position of the resin between respective non-defective bare chips.Type: GrantFiled: September 6, 2002Date of Patent: August 30, 2005Assignee: Sony CorporationInventors: Kazuo Nishiyama, Hiroshi Ozaki, Yuji Takaoka, Teruo Hirayama
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Publication number: 20050167851Abstract: A semiconductor part for component mounting, a mounting structure and a mounting method providing ample surplus wiring pitch and width between terminals in order to improve the strength of the connection with the printed circuit board in view of the recent trends towards a greater number of pins and greater component mounting density on printed circuit boards or substrates. A semiconductor component for mounting has area terminals comprised of area terminals mounted on the outer circumferential side and area terminals mounted on the inner circumferential side of the board. The area terminals on the outer circumferential side of the board are arranged with a larger pitch and or diameter than the area terminals on the inner circumferential side.Type: ApplicationFiled: March 18, 2005Publication date: August 4, 2005Inventor: Kazuo Nishiyama
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Patent number: 6919227Abstract: A semiconductor part for component mounting, a mounting structure and a mounting method providing ample surplus wiring pitch and width between terminals in order to improve the strength of the connection with the printed circuit board in view of the recent trends towards a greater number of pins and greater component mounting density on printed circuit boards or substrates. A semiconductor component for mounting has area terminals comprised of area terminals mounted on the outer circumferential side and area terminals mounted on the inner circumferential side of the board. The area terminals on the outer circumferential side of the board are arranged with a larger pitch and or diameter than the area terminals on the inner circumferential side.Type: GrantFiled: July 31, 2002Date of Patent: July 19, 2005Assignee: Sony CorporationInventor: Kazuo Nishiyama
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Patent number: 6841454Abstract: In order to have a thin type semiconductor chips featuring a high yield and a low cost in production, an excellent packaging reliability, and a robust structure against damages, there is provided a method of manufacturing LSI chips, comprising the steps of: pasting on a substrate an adhesive sheet which retains its adhesive strength prior to a processing, then loses it after the processing; bonding non-defective LSI chips on the adhesive sheet, with their device surfaces facing downward; uniformly coating an insulating film on the non-defective LSI chips; uniformly grinding the insulating film to a level of the bottom surfaces of these LSI chips; applying a predetermined process to the adhesive sheet to weaken its adhesive strength thereof so as to peel off a pseudo wafer on which the non-defective LSI chips are bonded; and dicing the LSI chips into a discrete non-defective electronic component by cutting the pseudo wafer.Type: GrantFiled: August 9, 2002Date of Patent: January 11, 2005Assignee: Sony CorporationInventor: Kazuo Nishiyama
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Publication number: 20030092252Abstract: A method of manufacturing the semiconductor chips comprises the steps of: pasting on a substrate an adhesive sheet having a property to retain its adhesive strength prior to a processing, then lose its adhesive strength after the processing; fixing a plurality of non-defective bare chips on this adhesive sheet, with their Al electrode pad surfaces facing down; coating a resin on a whole area other than the Al electrode pad surfaces of the plurality of non-defective bare chips including interspaces therebetween; applying a predetermined process to the adhesive sheet to weaken its adhesive strength of the adhesive sheet; peeling off a pseudo wafer bonding non-defective bare chips; and dicing the plurality of non-defective bare chips into a discrete non-defective electronic part by cutting the pseudo wafer at a position of the resin between respective non-defective bare chips.Type: ApplicationFiled: September 6, 2002Publication date: May 15, 2003Inventors: Kazuo Nishiyama, Hiroshi Ozaki, Yuji Takaoka, Teruo Hirayama
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Patent number: 6534875Abstract: A semiconductor part for component mounting, a mounting structure and a mounting method providing ample surplus wiring pitch and width between terminals in order to improve the strength of the connection with the printed circuit board in view of the recent trends towards a greater number of pins and greater component mounting density on printed circuit boards or substrates. A semiconductor component for mounting has area terminals comprised of area terminals mounted on the outer circumferential side and area terminals mounted on the inner circumferential side of the board. The area terminals on the outer circumferential side of the board are arranged with a larger pitch and or diameter than the area terminals on the inner circumferential side.Type: GrantFiled: September 17, 1999Date of Patent: March 18, 2003Assignee: Sony CorporationInventor: Kazuo Nishiyama
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Publication number: 20020195722Abstract: A semiconductor part for component mounting, a mounting structure and a mounting method providing ample surplus wiring pitch and width between terminals in order to improve the strength of the connection with the printed circuit board in view of the recent trends towards a greater number of pins and greater component mounting density on printed circuit boards or substrates. A semiconductor component for mounting has area terminals comprised of area terminals mounted on the outer circumferential side and area terminals mounted on the inner circumferential side of the board. The area terminals on the outer circumferential side of the board are arranged with a larger pitch and or diameter than the area terminals on the inner circumferential side.Type: ApplicationFiled: July 31, 2002Publication date: December 26, 2002Inventor: Kazuo Nishiyama
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Publication number: 20020192867Abstract: In order to have a thin type semiconductor chips featuring a high yield and a low cost in production, an excellent packaging reliability, and a robust structure against damages, there is provided a method of manufacturing LSI chips, comprising the steps of: pasting on a substrate an adhesive sheet which retains its adhesive strength prior to a processing, then loses it after the processing; bonding non-defective LSI chips on the adhesive sheet, with their device surfaces facing downward; uniformly coating an insulating film on the non-defective LSI chips; uniformly grinding the insulating film to a level of the bottom surfaces of these LSI chips; applying a predetermined process to the adhesive sheet to weaken its adhesive strength thereof so as to peel off a pseudo wafer on which the non-defective LSI chips are bonded; and dicing the LSI chips into a discrete non-defective electronic component by cutting the pseudo wafer.Type: ApplicationFiled: August 9, 2002Publication date: December 19, 2002Inventor: Kazuo Nishiyama
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Publication number: 20020152610Abstract: An electronic circuit device of a three-dimensional mounting mode capable of being produced by a simple method while suppressing the production costs and of a structure resistant to external stress, including first-mounting-board wiring portions formed on a first mounting board, first mounting parts mounted on the first mounting board, bumps formed on the first mounting board connecting to the first-mounting-board wiring portion, a protective layer formed covering the first mounting parts so that at least the portions near the tops of the bumps are exposed, a second mounting board stacked as an upper layer of the protective layer, second-mounting-board wiring portions formed on the second mounting board in order to connect to the bumps, and second mounting parts mounted connecting to the second-mounting-board wiring portions on the second mounting board at the surface of the second mounting board opposite to the protective layer side, and a method of production of the same.Type: ApplicationFiled: June 12, 2002Publication date: October 24, 2002Applicant: SONY CORPORATIONInventors: Kazuo Nishiyama, Yoshiyuki Yanagisawa, Toshiharu Yanagida, Masashi Enda, Yoshitaka Yoshino, Yuichi Takai, Kiyoshi Hasegawa