Patents by Inventor Kazuo Numasawa

Kazuo Numasawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Address decoder for a synchronous type memory capable of preventing multi-wordline selection
    Patent number: 6144612
    Abstract: Address decoder of the present invention includes a latch circuit for latching an address signal, a logical circuit for decoding output signal from the latching circuit and a decoding circuit for decoding an output signal from the logical circuit. The address signals are inputted to the latch circuit during a time period in which a clock signal is at a first level and latched during a time period in which the clock signal is at a second level. The logical circuits unconditionally initialize the output signal from the latch circuit when the clock signal being at first level.
    Type: Grant
    Filed: February 17, 2000
    Date of Patent: November 7, 2000
    Assignee: NEC Corporation
    Inventor: Kazuo Numasawa