Abstract: A controlling unit disposed in a PLL circuit controls a phase interpolator to gradually change a phase shift amount applied to a phase shift signal C_PS by a unit of basic delay amount ? at a timing predetermined in accordance with a modulation profile of an SSC. Further, the controlling unit controls a total phase shift amount applied to the phase shift signal C_PS output from the phase interpolator in one period of a feedback clock signal C_FB obtained by dividing frequency of the phase shift signal C_PS in a way that a difference between the total phase shift amount and a total phase shift amount in a previous one period of C_FB is always equal to or less than the basic delay amount ?.

Abstract: A controlling unit disposed in a PLL circuit controls a phase interpolator to gradually change a phase shift amount applied to a phase shift signal C_PS by a unit of basic delay amount ? at a timing predetermined in accordance with a modulation profile of an SSC. Further, the controlling unit controls a total phase shift amount applied to the phase shift signal C_PS output from the phase interpolator in one period of a feedback clock signal C_FB obtained by dividing frequency of the phase shift signal C_PS in a way that a difference between the total phase shift amount and a total phase shift amount in a previous one period of C_FB is always equal to or less than the basic delay amount ?.

Abstract: A controlling unit disposed in a PLL circuit controls a phase interpolator to gradually change a phase shift amount applied to a phase shift signal C_PS by a unit of basic delay amount ? at a timing predetermined in accordance with a modulation profile of an SSC. Further, the controlling unit controls a total phase shift amount applied to the phase shift signal C_PS output from the phase interpolator in one period of a feedback clock signal C_FB obtained by dividing frequency of the phase shift signal C_PS in a way that a difference between the total phase shift amount and a total phase shift amount in a previous one period of C_FB is always equal to or less than the basic delay amount ?.

Abstract: A spread spectrum clock generator capable of generating a smooth spread spectrum clock while suppressing an increase in the size of the circuitry includes a phase interpolator, receiving a clock signal from a clock input terminal and a control signal (an up signal and/or down signal) are input, for adjusting the phase of an output clock signal in accordance with the control signal and outputting the resultant clock signal, and a control circuit for counting the clock signal that enters from the clock input terminal and outputting the control signal to the phase interpolator, the control signal varying the phase of the output clock signal based upon the count result. The phase of the output clock signal from the phase interpolator varies with time and is frequency-modulated within a prescribed frequency range.

Abstract: A controlling unit disposed in a PLL circuit controls a phase interpolator to gradually change a phase shift amount applied to a phase shift signal C_PS by a unit of basic delay amount ? at a timing predetermined in accordance with a modulation profile of an SSC. Further, the controlling unit controls a total phase shift amount applied to the phase shift signal C_PS output from the phase interpolator in one period of a feedback clock signal C_FB obtained by dividing frequency of the phase shift signal C_PS in a way that a difference between the total phase shift amount and a total phase shift amount in a previous one period of C_FB is always equal to or less than the basic delay amount ?.

Abstract: Implementing maintenance of a higher speed with fewest possible additional circuits while suppressing deterioration in characteristics of a clock buffer caused by an offset voltage. In a clock buffer circuit comprising a differential amplifier including a pair of load resistances, a pair of differential stage transistors, a constant current source transistor for supplying an operating current to the differential stage transistors, and a bias circuit for supplying to the constant current source transistor a bias voltage according to the resistance value of the load resistances, the bias circuit generates the bias voltage so controlled that the voltage gain of the clock buffer circuit becomes a predetermined value with respect to a variation of the resistance value of the load resistances.

Abstract: Disclosed is a spread spectrum clock generator comprising a phase interpolator, which receives a clock signal from a clock input terminal and a control signal (an up signal and/or down signal), for adjusting the phase of an output clock signal in accordance with said control signal and outputting the resultant clock signal, and a control circuit receiving and counting the clock signal that enters from the clock input terminal and outputting said control signal (up signal or down signal), which is for varying the phase of the output clock signal based upon the result of the count, to the phase interpolator. The phase of the output clock signal from the phase interpolator varies with time and the output clock signal is frequency-modulated within a prescribed frequency range.

Abstract: Disclosed is a spread spectrum clock generator comprising a phase interpolator, which receives a clock signal from a clock input terminal and a control signal (an up signal and/or down signal), for adjusting the phase of an output clock signal in accordance with said control signal and outputting the resultant clock signal, and a control circuit receiving and counting the clock signal that enters from the clock input terminal and outputting said control signal (up signal or down signal), which is for varying the phase of the output clock signal based upon the result of the count, to the phase interpolator. The phase of the output clock signal from the phase interpolator varies with time and the output clock signal is frequency-modulated within a prescribed frequency range.

Abstract: Implementing maintenance of a higher speed with fewest possible additional circuits while suppressing deterioration in characteristics of a clock buffer caused by an offset voltage. In a clock buffer circuit comprising a differential amplifier including a pair of load resistances, a pair of differential stage transistors, a constant current source transistor for supplying an operating current to the differential stage transistors, and a bias circuit for supplying to the constant current source transistor a bias voltage according to the resistance value of the load resistances, the bias circuit generates the bias voltage so controlled that the voltage gain of the clock buffer circuit becomes a predetermined value with respect to a variation of the resistance value of the load resistances.

Abstract: A spread spectrum clock generator capable of generating a smooth spread spectrum clock while suppressing an increase in the size of the circuitry includes a phase interpolator, receiving a clock signal from a clock input terminal and a control signal (an up signal and/or down signal) are input, for adjusting the phase of an output clock signal in accordance with the control signal and outputting the resultant clock signal, and a control circuit for counting the clock signal that enters from the clock input terminal and outputting the control signal to the phase interpolator, the control signal varying the phase of the output clock signal based upon the count result. The phase of the output clock signal from the phase interpolator varies with time and is frequency-modulated within a prescribed frequency range.

Abstract: An insulated-gate type field-effect transistor (MOST) analog switching circuit which has improved capacitance compensation to provide high speed, low transient noise operation and which is readily implemented as an integrated circuit comprises a switching MOST coupled between an analog signal input terminal and an output terminal, and two series connected compensation MOSTs which are substantially the same size as the switching MOST. The compensation MOSTs are connected so as to function as compensation capacitors and the series circuit is connected between the output terminal of the switching circuit and a source of pulses of opposite phase to the switching pulses applied to the gate of the switching MOST. The compensation MOSTs can be interconnected in different ways to form the series circuit, but gate-to-gate interconnection is preferred where the junction capacitance between the source-drain and substrate is not negligible with respect to the gate capacitance.

Abstract: A semiconductor device has a first insulating film formed on a semiconductor substrate. A first group of parallel first unit resistor elements are made of a first layer of polycrystalline silicon and formed on and attached to the first insulating film. A second insulating film is formed over the first unit resistor elements and the surface of the first insulating film which is between the first unit resistor elements. A second group of parallel second unit resistor elements are made of a second layer of polycrystalline silicon which are formed on the second insulating film. Each of the resistor elements in both groups is formed with contact portions at opposite ends thereof.