Patents by Inventor Kazuo Ohno

Kazuo Ohno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7657660
    Abstract: The present invention provides an input/output device capable of bringing a per-unit input/output circuit into a simple configuration without impairing reliability even when logic levels opposite in polarity are outputted between input/output devices made conductive to the outside. The input/output device is equipped with one reference port Pk selected from a port group which inputs and outputs signals, target ports Pt selected from other than the reference port of the port group, and a conduction detector which detects that conduction is made between input/output terminals for the reference port Pk and the target ports Pt.
    Type: Grant
    Filed: February 2, 2007
    Date of Patent: February 2, 2010
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Kazuya Taniguchi, Osamu Matsuura, Kazuo Ohno
  • Publication number: 20070276964
    Abstract: The present invention provides an input/output device capable of bringing a per-unit input/output circuit into a simple configuration without impairing reliability even when logic levels opposite in polarity are outputted between input/output devices made conductive to the outside. The input/output device is equipped with one reference port Pk selected from a port group which inputs and outputs signals, target ports Pt selected from other than the reference port of the port group, and a conduction detector which detects that conduction is made between input/output terminals for the reference port Pk and the target ports Pt.
    Type: Application
    Filed: February 2, 2007
    Publication date: November 29, 2007
    Inventors: Kazuya Taniguchi, Osamu Matsuura, Kazuo Ohno
  • Patent number: 5680064
    Abstract: A first level converter is provided with an input transistor circuit and an output transistor circuit. The input transistor circuit is supplied with power from a first power source and outputs a complementary signal on the basis of an input signal. The output transistor circuit is supplied with power from a second power source, and amplifies and outputs the complementary signal. A second level converter is provided with a pulse generating circuit and a signal output circuit. The pulse generating circuit is supplied with power from the first driving power source, and generates a one-shot pulse signal. The signal output circuit is supplied with power from the second driving power source, latches the one-shot pulse signal and outputs the signal. The semiconductor integrated circuit is provided with a first circuit system, a level conversion circuit and a second circuit system. The first circuit system is driven by being supplied with power from the first driving power source.
    Type: Grant
    Filed: May 28, 1996
    Date of Patent: October 21, 1997
    Assignees: Fujitsu Limited, Fujitsu VLSI Limited, Kyushu Fujitsu Electronics Limited
    Inventors: Satoru Masaki, Akinori Yamamoto, Fusao Seki, Fumitaka Asami, Kazuo Ohno, Masao Imai, Shinya Udo