Patents by Inventor Kazuo Okada

Kazuo Okada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240346641
    Abstract: A video confirmation computer for confirming video related to robot operation includes a storage unit and a processor. The storage unit stores information on the position of the electric motor that drives a link body of the robot received from the controller of the robot and information on the video obtained by a camera attached to the robot. The processor makes at least one of the video confirmation computer itself and a computer connected to the video confirmation computer display a model area and a video area side by side. In the model area, a two-dimensional or three-dimensional model reproducing the posture of the robot is displayed by computer graphics. In the video area, the video is displayed.
    Type: Application
    Filed: June 26, 2024
    Publication date: October 17, 2024
    Applicant: KAWASAKI JUKOGYO KABUSHIKI KAISHA
    Inventors: Shinya KITANO, Atsushi NAKAYA, Masaya YOSHIDA, Kazuo FUJIMORI, Hiroyuki OKADA
  • Patent number: 12100616
    Abstract: A method of manufacturing a semiconductor device includes: planarizing a surface of a substrate having a conductive material embedded in a first hole so as to expose the conductive material embedded in the first hole, wherein the first hole is formed in a region which is on an insulating film laminated on the substrate and is surrounded by a spacer film; laminating a mask film on the surface of the substrate; forming a second hole in the mask film such that at least a portion of an upper surface of the conductive material embedded in the first hole is exposed; embedding the conductive material in the second hole; and removing the mask film.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: September 24, 2024
    Assignee: Tokyo Electron Limited
    Inventors: Kazuo Kibi, Shigetsugu Fujita, Kenji Suzuki, Mitsuhiro Okada
  • Patent number: 12045972
    Abstract: A video confirmation computer for confirming video related to robot operation includes a storage unit and a processor. The storage unit stores information on the position of the electric motor that drives a link body of the robot received from the controller of the robot and information on the video obtained by a camera attached to the robot. The processor makes at least one of the video confirmation computer itself and a computer connected to the video confirmation computer display a model area and a video area side by side. In the model area, a two-dimensional or three-dimensional model reproducing the posture of the robot is displayed by computer graphics. In the video area, the video is displayed.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: July 23, 2024
    Assignee: KAWASAKI JUKOGYO KABUSHIKI KAISHA
    Inventors: Shinya Kitano, Atsushi Nakaya, Masaya Yoshida, Kazuo Fujimori, Hiroyuki Okada
  • Patent number: 12040295
    Abstract: Implementations of semiconductor devices may include a die having a first side and a second side, a contact pad coupled to the first side of the die, and a metal layer coupled to the second side of the die. A thickness of the die may be no more than four times a thickness of the metal layer.
    Type: Grant
    Filed: May 14, 2021
    Date of Patent: July 16, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. Seddon, Takashi Noma, Kazuo Okada, Hideaki Yoshimi, Naoyuki Yomoda, Yusheng Lin
  • Patent number: 11839835
    Abstract: A simulated moving-bed type chromatographic separation method separating a weakly adsorptive component, a strongly adsorptive component, and an intermediately adsorptive component, with eluents by using a circulation system in which a plurality of unit packed columns packed with an adsorbent are connected in series and in an endless form via pipes in which a feed solution supply port F, two or more eluent supply ports D corresponding to the eluents, an extraction port A of a fraction containing the weakly adsorptive component, an extraction port B of a fraction containing the intermediately adsorptive component, and an extraction port C of a fraction containing the strongly adsorptive component are provided in the pipes of the circulation system, and positions of the ports F, A, B, and C are set to have a specified relationship.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: December 12, 2023
    Assignee: ORGANO CORPORATION
    Inventors: Kazuo Okada, Masahiro Ogino, Kohei Sato, Masaki Tsuruta, Toshiki Miyajima
  • Publication number: 20230338871
    Abstract: A simulated moving-bed type chromatographic separation method including separating a weakly adsorptive component, a strongly adsorptive component, and an intermediately adsorptive component that has adsorptive property intermediate between the two components, with respect to an adsorbent, with two or more kinds of eluents by using a circulation system in which a plurality of unit packed columns each packed with an adsorbent are connected in series and in an endless form via pipes, the weakly adsorptive component, the strongly adsorptive component, and the intermediately adsorptive component being contained in a feed solution, wherein a feed solution supply port, eluent suply ports and a plurality of extraction ports are provided on the pipes of the circulation system, and positions of the feed solution supply port and the plurality of extraction ports are set to have a specified relationship; and a chromatographic separation system suitable for implementing the chromatographic separation method.
    Type: Application
    Filed: May 7, 2021
    Publication date: October 26, 2023
    Applicant: ORGANO CORPORATION
    Inventors: Masahiro OGINO, Kazuo OKADA, Masaki TSURUTA, Kohei SATO, Toshiki MIYAJIMA
  • Patent number: 11735497
    Abstract: A method for making an integrated passive device (IPD) die includes grinding a backside of a semiconductor substrate to reduce a thickness of a central portion of the semiconductor substrate while leaving a mechanical support ring on an outer portion of the substrate, and forming a through-substrate via (TSV) from the backside of the substrate. The TSV defines interconnect access to at least one passive component embedded in an insulator material disposed on a front surface of the semiconductor substrate. The substrate has a thickness less than three-quarters of an original thickness of the substrate.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: August 22, 2023
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Takashi Noma, Hideyuki Inotsume, Kazuo Okada
  • Patent number: 11728424
    Abstract: According to an aspect, a semiconductor device for integrating multiple transistors includes a wafer substrate including a first region and a second region. The first region defines at least a portion of at least one first transistor. The second region defines at least a portion of at least one second transistor. The semiconductor device includes an isolation area located between the first region and the second region, at least one terminal of the at least one first transistor contacting the first region of the wafer substrate, at least one terminal of the at least one second transistor contacting the second region of the wafer substrate, and an encapsulation material, where the encapsulation material includes a portion located within the isolation area.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: August 15, 2023
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Takashi Noma, Yusheng Lin, Kazuo Okada, Hideaki Yoshimi, Shunsuke Yasuda
  • Publication number: 20220131002
    Abstract: According to an aspect, a semiconductor device for integrating multiple transistors includes a wafer substrate including a first region and a second region. The first region defines at least a portion of at least one first transistor. The second region defines at least a portion of at least one second transistor. The semiconductor device includes an isolation area located between the first region and the second region, at least one terminal of the at least one first transistor contacting the first region of the wafer substrate, at least one terminal of the at least one second transistor contacting the second region of the wafer substrate, and an encapsulation material, where the encapsulation material includes a portion located within the isolation area.
    Type: Application
    Filed: October 26, 2020
    Publication date: April 28, 2022
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Takashi NOMA, Yusheng LIN, Kazuo OKADA, Hideaki YOSHIMI, Shunsuke YASUDA
  • Publication number: 20220032208
    Abstract: A simulated moving-bed type chromatographic separation method separating a weakly adsorptive component, a strongly adsorptive component, and an intermediately adsorptive component, with eluents by using a circulation system in which a plurality of unit packed columns packed with an adsorbent are connected in series and in an endless form via pipes in which a feed solution supply port F, two or more eluent supply ports D corresponding to the eluents, an extraction port A of a fraction containing the weakly adsorptive component, an extraction port B of a fraction containing the intermediately adsorptive component, and an extraction port C of a fraction containing the strongly adsorptive component are provided in the pipes of the circulation system, and positions of the ports F, A, B, and C are set to have a specified relationship.
    Type: Application
    Filed: October 8, 2019
    Publication date: February 3, 2022
    Applicant: ORGANO CORPORATION
    Inventors: Kazuo OKADA, Masahiro OGINO, Kohei SATO, Masaki TSURUTA, Toshiki MIYAJIMA
  • Patent number: 11114402
    Abstract: Implementations of semiconductor devices may include a die having a first side and a second side, a contact pad coupled to the first side of the die, and a metal layer coupled to the second side of the die. A thickness of the die may be no more than four times a thickness of the metal layer.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: September 7, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. Seddon, Takashi Noma, Kazuo Okada, Hideaki Yoshimi, Naoyuki Yomoda, Yusheng Lin
  • Publication number: 20210272920
    Abstract: Implementations of semiconductor devices may include a die having a first side and a second side, a contact pad coupled to the first side of the die, and a metal layer coupled to the second side of the die. A thickness of the die may be no more than four times a thickness of the metal layer.
    Type: Application
    Filed: May 14, 2021
    Publication date: September 2, 2021
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. SEDDON, Takashi NOMA, Kazuo OKADA, Hideaki YOSHIMI, Naoyuki YOMODA, Yusheng LIN
  • Patent number: 10839648
    Abstract: A gaming machine having a display that displays a determined screen including a character, during execution of a game, a touch panel sensor, disposed above the display, that is capable of detecting the contact position, the position of the character contacted by a player, and a CPU that determines the contact position of the character as well as the contact mode, and that displays an image on the display, that is changed based on the result of this determination.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: November 17, 2020
    Assignee: Universal Entertainment Corporation (nee Aruze Corporation)
    Inventors: Kazuo Okada, Hirobumi Toyoda
  • Publication number: 20200126894
    Abstract: A method for making an integrated passive device (IPD) die includes grinding a backside of a semiconductor substrate to reduce a thickness of a central portion of the semiconductor substrate while leaving a mechanical support ring on an outer portion of the substrate, and forming a through-substrate via (TSV) from the backside of the substrate. The TSV defines interconnect access to at least one passive component embedded in an insulator material disposed on a front surface of the semiconductor substrate. The substrate has a thickness less than three-quarters of an original thickness of the substrate.
    Type: Application
    Filed: December 20, 2019
    Publication date: April 23, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Takashi NOMA, Hideyuki INOTSUME, Kazuo OKADA
  • Patent number: 10535585
    Abstract: In one general aspect, an integrated passive device (IPD) die includes at least one passive component that is embedded in an insulator material disposed on a front surface of a substrate. The IPD die includes a through-substrate via (TSV) extending from the backside of the substrate toward the front surface of the substrate. The TSV defines interconnect access to at least one passive component embedded in the insulator material disposed on the front surface of the substrate. The substrate has a thickness less than three-quarters of an original thickness of the substrate.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: January 14, 2020
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Takashi Noma, Hideyuki Inotsume, Kazuo Okada
  • Publication number: 20190267344
    Abstract: Implementations of semiconductor devices may include a die having a first side and a second side, a contact pad coupled to the first side of the die, and a metal layer coupled to the second side of the die. A thickness of the die may be no more than four times a thickness of the metal layer.
    Type: Application
    Filed: February 23, 2018
    Publication date: August 29, 2019
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. SEDDON, Takashi NOMA, Kazuo OKADA, Hideaki YOSHIMI, Naoyuki YOMODA, Yusheng LIN
  • Publication number: 20190172316
    Abstract: A gaming machine having a display that displays a determined screen including a character, during execution of a game, a touch panel sensor, disposed above the display, that is capable of detecting the contact position, the position of the character contacted by a player, and a CPU that determines the contact position of the character as well as the contact mode, and that displays an image on the display, that is changed based on the result of this determination.
    Type: Application
    Filed: February 8, 2019
    Publication date: June 6, 2019
    Inventors: Kazuo OKADA, Hirobumi TOYODA
  • Patent number: 10242533
    Abstract: A gaming machine having a display that displays a determined screen including a character, during execution of a game, a touch panel sensor, disposed above the display, that is capable of detecting the contact position, the position of the character contacted by a player, and a CPU that determines the contact position of the character as well as the contact mode, and that displays an image on the display, that is changed based on the result of this determination.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: March 26, 2019
    Assignee: Universal Entertainment Corporation
    Inventors: Kazuo Okada, Hirobumi Toyoda
  • Publication number: 20190067164
    Abstract: In one general aspect, an integrated passive device (IPD) die includes at least one passive component that is embedded in an insulator material disposed on a front surface of a substrate. The IPD die includes a through-substrate via (TSV) extending from the backside of the substrate toward the front surface of the substrate. The TSV defines interconnect access to at least one passive component embedded in the insulator material disposed on the front surface of the substrate. The substrate has a thickness less than three-quarters of an original thickness of the substrate.
    Type: Application
    Filed: November 15, 2017
    Publication date: February 28, 2019
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Takashi NOMA, Hideyuki INOTSUME, Kazuo OKADA
  • Patent number: 10134230
    Abstract: The present application provides a game playing information integration system which is capable of objectively performing selection and/or settings according to preference of a player, particularly fixed customers, and thereby capable of effectively introducing a gaming machine to invoke demands of players as users and managers of gaming facilities in a well-balanced manner from a result obtained by logically analyzing the gaming machine. (a) Game playing period at one time of each player in gaming machine unit, (b) change in balance over time of player in a game playing period, (c) operation time of the gaming machine unit, and (d) data relating to profit of a shop side by the gaming machine are generated, the degree of satisfaction of player is computed based on (a) and (b), and the degree of satisfaction of a shop side is computed based on (c) and (d).
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: November 20, 2018
    Assignees: Universal Entertainment Corporation, Aruze Gaming America, Inc.
    Inventors: Kazuo Okada, Kengo Takeda