Abstract: The voltage generator circuit according to the invention has a first negative potential generator circuit to generate a first clock signal going negative and oscillating at negative voltage in response to a first clock signal oscillating at positive voltage, a second negative potential generator circuit to generate, in response to a second clock signal oscillating at positive voltage, a second clock signal going negative and oscillating at negative voltage and having an amplitude greater than the amplitude voltage of the first clock signal going negative, and an output circuit to deliver the lowest voltage of the first clock signal in response to the second clock signal going negative.

Abstract: The power consumption of a semiconductor device capable of performing any one of a plurality of functions selectively according to whether a predetermined bonding pad thereof is bonded to a power source line or a ground line is reduced during an idle time. The potential of the bonding pad when the latter is in a floating state is driven to a certain level by a current flowing through a P-type MOS transistor having a relatively large driving capability during a predetermined time from initial application of a power supply voltage to the semiconductor device. Thereafter, the bonding pad is biased by a P type MOS transistor having a relatively smaller driving capability.

Abstract: First and second memory cell arrays are incorporated in a semiconductor memory device for storing n-bit data codes and 2n-bit data codes, and first and second data input/ output units are respectively provided on the left side of the first memory cell array for the n-bits of the 2n-bit data codes written into or read out from the first memory cell array and on the right side of the second memory cell array for the n-bit data codes and the other n-bits of the 2n-bit data codes written into or read out from the second memory cell array, wherein a third data input/ output unit is further provided on the right side of the first memory cell array for the n-bit data codes written into or read out from the first memory cell array instead of a data propagation path from the second data input/ output unit to the first memory cell array so that the n-bit data codes and the 2n-bit data codes are written and read out at the same speed.