Abstract: A scan IC includes a switch circuit and a logic circuit. The switch circuit includes first and second transistors and a level shift circuit. First and second control signals that change between a logical “1” and a logical “0” are applied to an input terminal of the logic circuit. The logic circuit applies a third control signal to the first transistor and applies a fourth control signal to the second transistor based on the applied first and second control signals. A detection circuit is connected to the input terminal of the logic circuit. An abnormality of the scan IC is detected by the detection circuit.

Abstract: A scan IC includes a switch circuit and a logic circuit. The switch circuit includes first and second transistors and a level shift circuit. First and second control signals that change between a logical “1” and a logical “0” are applied to an input terminal of the logic circuit. The logic circuit applies a third control signal to the first transistor and applies a fourth control signal to the second transistor based on the applied first and second control signals. A detection circuit is connected to the input terminal of the logic circuit. An abnormality of the scan IC is detected by the detection circuit.

Abstract: A first group of data drivers is connected to a sub-field processor, a first power recovery circuit, and a PDP, and a second group of data drivers is connected to a sub-field processor, a second power recovery circuit, and a PDP. The first and second groups of data drivers apply to the PDP data pulses that differ in phases. The first and second power recovery circuits generate a voltage for generating the data pulses to the first and second groups of data drivers due to LC resonance, and discharge and recover charges to and from the PDP. Recovery potentials of recovery capacitors in the first and second power recovery circuits are changed depending on the number of times of switching between discharges and non-discharges of discharge cells in the PDP.

Abstract: In a driving device of a plasma display panel including switch circuits (Q1, Q2) that selectively connect either a first node (N1) or a second node (N2) to a scan electrode (SC1), a voltage hold circuit (200) that is provided between the first node (N1) and a third node (N3) for holding a voltage between the first node (N1) and the second node (N2) to a first voltage (Vscn), a protection circuit (300) that is provided between the second node (N2) and the third node (N3), and a potential of the first node (N1) being changed, the protection circuit (300) includes a protective resistance (R1), a rectification circuit composed of a capacitor (C1), a charge restriction resistance (R2), and a diode (Da) connected in parallel to the protective resistance (R1), two discharge resistances (R3, R4) connected in parallel to the capacitor (C1), and a transistor (Q10) that generates an abnormality detection signal (SOS) based on a potential of a connection point (N7) of the two discharge resistances (R3, R4).

Abstract: A first group of data drivers is connected to a sub-field processor, a first power recovery circuit, and a PDP, and a second group of data drivers is connected to a sub-field processor, a second power recovery circuit, and a PDP. The first and second groups of data drivers apply to the PDP data pulses that differ in phases. The first and second power recovery circuits generate a voltage for generating the data pulses to the first and second groups of data drivers due to LC resonance, and discharge and recover charges to and from the PDP. Recovery potentials of recovery capacitors in the first and second power recovery circuits are changed depending on the number of times of switching between discharges and non-discharges of discharge cells in the PDP.

Abstract: In each of sub-fields on each of lines in a plasma display device, it is judged whether or not all of a plurality of discharge cells on the line or the display cells whose number is not less than a predetermined number do not emit light, and at least one of a voltage applied to a scan electrode and a voltage applied to a sustain electrode on the line are kept at predetermined levels when all of the discharge cells or the discharge cells whose number is not less than the predetermined number do not emit light, or a pulse having the same phase as that of a sustain pulse applied to the sustain electrode 13 is periodically applied in place of a sustain pulse applied to the scan electrode 12 corresponding to the line, to decrease a charge or discharge current as well as to reduce the generation of electromagnetic waves.

Abstract: In each of sub-fields on each of lines in a plasma display device, it is judged whether or not all of a plurality of discharge cells on the line or the display cells whose number is not less than a predetermined number do not emit light, and at least one of a voltage applied to a scan electrode and a voltage applied to a sustain electrode on the line are kept at predetermined levels when all of the discharge cells or the discharge cells whose number is not less than the predetermined number do not emit light, or a pulse having the same phase as that of a sustain pulse applied to the sustain electrode 13 is periodically applied in place of a sustain pulse applied to the scan electrode 12 corresponding to the line, to decrease a charge or discharge current as well as to reduce the generation of electromagnetic waves.