Abstract: Disclosed herein is a memory controller controlling data transfer between a host system and a flash memory. The memory controller is configured to limit a data transfer rate in a second period following a first period to a predetermined rate lower than a maximum rate when the data transfer rate in a first period satisfies a predetermined condition.

Abstract: Disclosed herein is a memory controller controlling data transfer between a host system and a flash memory. The memory controller is configured to operate on one of a plurality of operation states including first and second operation states. In the first operation state, a first memory area included in the flash memory is used in a first storage mode that stores information of less than n bits in one cell, and a second memory area included in the flash memory is used in a second storage mode that stores information of n bits or more in one cell. In the second operation state, the first memory area is used in the second storage mode, and the second memory area is used in the first storage mode.

Abstract: Disclosed herein is a memory controller controlling data transfer between a host system and a flash memory. The memory controller is configured to operate on one of a plurality of operation states including first and second operation states. In the first operation state, a first memory area included in the flash memory is used in a first storage mode that stores information of less than n bits in one cell, and a second memory area included in the flash memory is used in a second storage mode that stores information of n bits or more in one cell. In the second operation state, the first memory area is used in the second storage mode, and the second memory area is used in the first storage mode.

Abstract: Disclosed herein is a memory controller controlling data transfer between a host system and a flash memory. The memory controller is configured to limit a data transfer rate in a second period following a first period to a predetermined rate lower than a maximum rate when the data transfer rate in a first period satisfies a predetermined condition.

Abstract: A DQPSK mapping circuit is disclosed which comprises: a parallel decoding circuit having inputs for decoding first to 2Nth bits of input data and one symbol period prior I and Q data which are prior by one symbol period from the present decoding cycle thereof through the inputs and outputting serial first to Nth I and Q data of the present decoding period in parallel, N is a natural number; and a FF circuit for supplying the Nth I and Q data to the inputs as the one symbol period prior I and Q data in the succeeding decoding cycle of the parallel decoding circuit. The parallel decoding circuit may comprise first to Nth decoders, an Mth decoder out of the first to Nth decoders decoding 2Mth bit and (2M-1)th bits of the input data and outputs of (M-1)th decoder, M being a natural number and M.ltoreq.N, wherein the first decoder decodes the one symbol period prior I and Q data and the first and second bits of the input data.

Abstract: Received data representing voice information is subjected to Viterbi decoding to correct an error in the received data. Thereby, the received data is decoded into second data. A path metric is calculated to determine the second data during the Viterbi decoding. A decision is made as to whether or not at least one error is present in the second data by referring to a cyclic redundancy check code in the second data. The second data is discarded when it is decided that at least one error is present in the second data. A decision is made as to whether or not the calculated path metric exceeds a threshold value. The second data is discarded when it is decided that the path metric exceeds the threshold value. The second data is converted into sound when it is decided that at least one error is not present in the second data and that the path metric does not exceed the threshold value.

Abstract: A data receiving system has a radio frequency unit for demodulating a series of signals transmitted at a carrier wave frequency, a local oscillating unit for generating a demodulating frequency used for the demodulation of the series of signals, an equalizing unit for removing a distortion of the series of signals demodulated in the radio frequency unit, a phase shift estimating unit for taking out phase information from the series of signals, calculating a time changing rate of the phase information and estimating a phase shift caused by a difference between the carrier wave frequency and the demodulating frequency according to the time changing rate, and a correcting unit for correcting the series of signals transmitted from the equalizing unit according to the phase shift to remove the phase shift from the series of signals.