Patents by Inventor Kazuo Shimoyama
Kazuo Shimoyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140327041Abstract: A thin semiconductor wafer, on which a top surface structure and a bottom surface structure that form a semiconductor chip are formed, is affixed to a supporting substrate by a double-sided adhesive tape. Then, on the thin semiconductor wafer, a trench to become a scribing line is formed by wet anisotropic etching with a crystal face exposed so as to form a side wall of the trench. On the side wall of the trench with the crystal face thus exposed, an isolation layer for holding a reverse breakdown voltage is formed by ion implantation and low temperature annealing or laser annealing so as to be extended to the top surface side while being in contact with a p collector region as a bottom surface diffused layer. Then, laser dicing is carried out to neatly dice a collector electrode, formed on the p collector region, together with the p collector region, without presenting any excessive portions and any insufficient portions under the isolation layer.Type: ApplicationFiled: July 22, 2014Publication date: November 6, 2014Inventors: Kazuo SHIMOYAMA, Manabu TAKEI, Haruo NAKAZAWA
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Patent number: 8759870Abstract: On the top surface of a thin semiconductor wafer, top surface structures forming a semiconductor chip are formed. The top surface of the wafer is affixed to a supporting substrate with a double-sided adhesive tape. Then, from the bottom surface of the thin semiconductor wafer, a trench, which becomes a scribing line, is formed by wet anisotropic etching so that side walls of the trench are exposed. On the side walls of the trench with the crystal face exposed, an isolation layer with a conductivity type different from that of the semiconductor wafer for holding a reverse breakdown voltage is formed simultaneously with a collector region of the bottom surface diffused layer by ion implantation, followed by annealing with laser irradiation. The side walls form a substantially V-shaped or trapezoidal-shaped cross section, with an angle of the side wall relative to the supporting substrate being 30-70°. The double-sided adhesive tape is then removed from the top surface to produce semiconductor chips.Type: GrantFiled: June 28, 2010Date of Patent: June 24, 2014Assignee: Fuji Electric Co., Ltd.Inventors: Haruo Nakazawa, Kazuo Shimoyama, Manabu Takei
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Patent number: 8697558Abstract: On the top surface of a thin semiconductor wafer, top surface structures forming a semiconductor chip are formed. The top surface of the wafer is affixed to a supporting substrate with a double-sided adhesive tape. Then, from the bottom surface of the thin semiconductor wafer, a trench, which becomes a scribing line, is formed by wet anisotropic etching so that side walls of the trench are exposed. On the side walls of the trench with the crystal face exposed, an isolation layer with a conductivity type different from that of the semiconductor wafer for holding a reverse breakdown voltage is formed simultaneously with a collector region of the bottom surface diffused layer by ion implantation, followed by annealing with laser irradiation. The side walls form a substantially V-shaped or trapezoidal-shaped cross section, with an angle of the side wall relative to the supporting substrate being 30-70°. The double-sided adhesive tape is then removed from the top surface to produce semiconductor chips.Type: GrantFiled: October 8, 2009Date of Patent: April 15, 2014Assignee: Fuji Electric Co., Ltd.Inventors: Haruo Nakazawa, Kazuo Shimoyama, Manabu Takei
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Patent number: 8531007Abstract: A semiconductor device is disclosed which includes active section 100, edge termination section 110 having a voltage blocking structure and disposed around active section 100, and separation section 120 having a device separation structure and disposed around edge termination section 110. A surface device structure is formed on the first major surface of active section 100, trench 23 is formed in separation section 120 from the second major surface side, and p+-type separation region 24 is formed on the side wall of trench 23 such that p+-type separation region 24 is in contact with p-type channel stopper region 21 formed in the surface portion on the first major surface side and p-type collector layer 9 formed in the surface portion on the second major surface side. The semiconductor device and the method for manufacturing the semiconductor device according to the invention facilitate preventing the reverse blocking voltage from decreasing and shorten the manufacturing time of the semiconductor device.Type: GrantFiled: May 20, 2010Date of Patent: September 10, 2013Assignees: Octec, Inc., Fuji Electric Co., Ltd.Inventors: Katsuya Okumura, Hiroki Wakimoto, Kazuo Shimoyama, Tomoyuki Yamazaki
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Patent number: 8507327Abstract: Cutting work is performed on an n-semiconductor substrate (1) with an inverted trapezoid-shaped dicing blade to form grooves to be a second side walls (7). Bottom portions of the grooves are contacted with a p-diffusion layer (4) which is formed on a first principal plane (2) (front face) of the n-semiconductor substrate (1), so that the p-diffusion layer (4) is not cut. Then in the second side walls (7), a p-isolation layer (9) connected to a p-collector layer (8) and the p-diffusion layer (4) is formed. Since the p-diffusion layer (4) is not cut, a glass support substrate for supporting a wafer, and expensive adhesive, are not required, and therefore the p-isolation layer (4) can be formed at low cost.Type: GrantFiled: May 13, 2009Date of Patent: August 13, 2013Assignee: Fuji Electric Co., Ltd.Inventors: Yasuhiko Tsukamoto, Kazuo Shimoyama
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Publication number: 20120184083Abstract: A thin semiconductor wafer, on which a top surface structure and a bottom surface structure that form a semiconductor chip are formed, is affixed to a supporting substrate. Then, on the wafer, a trench to become a scribing line is formed with a crystal face exposed so as to form a side wall of the trench. On that side wall, an isolation layer for holding a reverse breakdown voltage is formed by ion implantation and low temperature annealing or laser annealing so as to be extended to the top surface side while being in contact with a p collector region as a bottom surface diffused layer. Then, laser dicing is carried out to dice a collector electrode, formed on the p collector region, together with the p collector region.Type: ApplicationFiled: January 18, 2012Publication date: July 19, 2012Applicant: FUJI ELECTRIC CO., LTD.Inventors: Kazuo SHIMOYAMA, Manabu TAKEI, Haruo NAKAZAWA
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Patent number: 8119496Abstract: A thin semiconductor wafer, on which a top surface structure and a bottom surface structure that form a semiconductor chip are formed, is affixed to a supporting substrate by a double-sided adhesive tape. Then, on the thin semiconductor wafer, a trench to become a scribing line is formed by wet anisotropic etching with a crystal face exposed so as to form a side wall of the trench. On the side wall of the trench with the crystal face thus exposed, an isolation layer for holding a reverse breakdown voltage is formed by ion implantation and low temperature annealing or laser annealing so as to be extended to the top surface side while being in contact with a p collector region as a bottom surface diffused layer. Then, laser dicing is carried out to neatly dice a collector electrode, formed on the p collector region, together with the p collector region, without presenting any excessive portions and any insufficient portions under the isolation layer.Type: GrantFiled: May 24, 2010Date of Patent: February 21, 2012Assignee: Fuji Electric Co., Ltd.Inventors: Kazuo Shimoyama, Manabu Takei, Haruo Nakazawa
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Publication number: 20110108883Abstract: Cutting work is performed on an n-semiconductor substrate (1) with an inverted trapezoid-shaped dicing blade to form grooves to be a second side walls (7). Bottom portions of the grooves are contacted with a p-diffusion layer (4) which is formed on a first principal plane (2) (front face) of the n-semiconductor substrate (1), so that the p-diffusion layer (4) is not cut. Then in the second side walls (7), a p-isolation layer (9) connected to a p-collector layer (8) and the p-diffusion layer (4) is formed. Since the p-diffusion layer (4) is not cut, a glass support substrate for supporting a wafer, and expensive adhesive, are not required, and therefore the p-isolation layer (4) can be formed at low cost.Type: ApplicationFiled: May 13, 2009Publication date: May 12, 2011Applicant: FUJI ELECTRIC SYSTEMS CO. LTD.Inventors: Yasuhiko Tsukamoto, Kazuo Shimoyama
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Publication number: 20110081752Abstract: A thin semiconductor wafer, on which a top surface structure and a bottom surface structure that form a semiconductor chip are formed, is affixed to a supporting substrate by a double-sided adhesive tape. Then, on the thin semiconductor wafer, a trench to become a scribing line is formed by wet anisotropic etching with a crystal face exposed so as to form a side wall of the trench. On the side wall of the trench with the crystal face thus exposed, an isolation layer for holding a reverse breakdown voltage is formed by ion implantation and low temperature annealing or laser annealing so as to be extended to the top surface side while being in contact with a p collector region as a bottom surface diffused layer. Then, laser dicing is carried out to neatly dice a collector electrode, formed on the p collector region, together with the p collector region, without presenting any excessive portions and any insufficient portions under the isolation layer.Type: ApplicationFiled: May 24, 2010Publication date: April 7, 2011Applicant: FUJI ELECTRIC SYSTEMS CO., LTD.Inventors: Kazuo SHIMOYAMA, Manabu TAKEI, Haruo NAKAZAWA
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Publication number: 20110006403Abstract: A semiconductor device is disclosed which includes active section 100, edge termination section 110 having a voltage blocking structure and disposed around active section 100, and separation section 120 having a device separation structure and disposed around edge termination section 110. A surface device structure is formed on the first major surface of active section 100, trench 23 is formed in separation section 120 from the second major surface side, and p+-type separation region 24 is formed on the side wall of trench 23 such that p+-type separation region 24 is in contact with p-type channel stopper region 21 formed in the surface portion on the first major surface side and p-type collector layer 9 formed in the surface portion on the second major surface side. The semiconductor device and the method for manufacturing the semiconductor device according to the invention facilitate preventing the reverse blocking voltage from decreasing and shorten the manufacturing time of the semiconductor device.Type: ApplicationFiled: May 20, 2010Publication date: January 13, 2011Applicant: FUJI ELECTRIC SYSTEMS CO. LTD.Inventors: Katsuya OKUMURA, Hiroki WAKIMOTO, Kazuo SHIMOYAMA, Tomoyuki YAMAZAKI
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Publication number: 20100264455Abstract: On the top surface of a thin semiconductor wafer, top surface structures forming a semiconductor chip are formed. The top surface of the wafer is affixed to a supporting substrate with a double-sided adhesive tape. Then, from the bottom surface of the thin semiconductor wafer, a trench, which becomes a scribing line, is formed by wet anisotropic etching so that side walls of the trench are exposed. On the side walls of the trench with the crystal face exposed, an isolation layer with a conductivity type different from that of the semiconductor wafer for holding a reverse breakdown voltage is formed simultaneously with a collector region of the bottom surface diffused layer by ion implantation, followed by annealing with laser irradiation. The side walls form a substantially V-shaped or trapezoidal-shaped cross section, with an angle of the side wall relative to the supporting substrate being 30-70°. The double-sided adhesive tape is then removed from the top surface to produce semiconductor chips.Type: ApplicationFiled: June 28, 2010Publication date: October 21, 2010Applicant: FUJI ELECTRIC HOLDINGS CO. LTDInventors: Haruo NAKAZAWA, Kazuo SHIMOYAMA, Manabu TAKEI
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Patent number: 7776672Abstract: On the top surface of a thin semiconductor wafer, top surface structures forming a semiconductor chip are formed. The top surface of the wafer is affixed to a supporting substrate with a double-sided adhesive tape. Then, from the bottom surface of the thin semiconductor wafer, a trench, which becomes a scribing line, is formed by wet anisotropic etching so that side walls of the trench are exposed. On the side walls of the trench with the crystal face exposed, an isolation layer with a conductivity type different from that of the semiconductor wafer for holding a reverse breakdown voltage is formed simultaneously with a collector region of the bottom surface diffused layer by ion implantation, followed by annealing with laser irradiation. The side walls form a substantially V-shaped or trapezoidal-shaped cross section, with an angle of the side wall relative to the supporting substrate being 30-70°. The double-sided adhesive tape is then removed from the top surface to produce semiconductor chips.Type: GrantFiled: March 27, 2006Date of Patent: August 17, 2010Assignee: Fuji Electric Systems Co., Ltd.Inventors: Haruo Nakazawa, Kazuo Shimoyama, Manabu Takei
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Patent number: 7741192Abstract: A thin semiconductor wafer, on which a top surface structure and a bottom surface structure that form a semiconductor chip are formed, is affixed to a supporting substrate by a double-sided adhesive tape. Then, on the thin semiconductor wafer, a trench to become a scribing line is formed by wet anisotropic etching with a crystal face exposed so as to form a side wall of the trench. On the side wall of the trench with the crystal face thus exposed, an isolation layer for holding a reverse breakdown voltage is formed by ion implantation and low temperature annealing or laser annealing so as to be extended to the top surface side while being in contact with a p collector region as a bottom surface diffused layer. Then, laser dicing is carried out to neatly dice a collector electrode, formed on the p collector region, together with the p collector region, without presenting any excessive portions and any insufficient portions under the isolation layer.Type: GrantFiled: August 19, 2005Date of Patent: June 22, 2010Assignee: Fuji Electric Systems Co., Ltd.Inventors: Kazuo Shimoyama, Manabu Takei, Haruo Nakazawa
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Publication number: 20100093164Abstract: On the top surface of a thin semiconductor wafer, top surface structures forming a semiconductor chip are formed. The top surface of the wafer is affixed to a supporting substrate with a double-sided adhesive tape. Then, from the bottom surface of the thin semiconductor wafer, a trench, which becomes a scribing line, is formed by wet anisotropic etching so that side walls of the trench are exposed. On the side walls of the trench with the crystal face exposed, an isolation layer with a conductivity type different from that of the semiconductor wafer for holding a reverse breakdown voltage is formed simultaneously with a collector region of the bottom surface diffused layer by ion implantation, followed by annealing with laser irradiation. The side walls form a substantially V-shaped or trapezoidal-shaped cross section, with an angle of the side wall relative to the supporting substrate being 30-70°. The double-sided adhesive tape is then removed from the top surface to produce semiconductor chips.Type: ApplicationFiled: October 8, 2009Publication date: April 15, 2010Applicant: FUJI ELECTRIC HOLDINGS CO., LTD.Inventors: Haruo NAKAZAWA, Kazuo SHIMOYAMA, Manabu TAKEI
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Patent number: 7557007Abstract: The method for manufacturing a semiconductor device according to the invention includes forming a thick silicon oxide film uniformly in a trench. Argon ions or the like implanted obliquely into the trench to form an ion implanted damaged region selectively in the portion of the silicon oxide film on the trench sidewall utilizing the shadowing effects of the oblique ion implantation. The silicon oxide film is wet etched to selectively remove the silicon oxide film in the ion implanted damaged region utilizing the etching rate difference, wherein the etching rate is faster in the damaged region than in the undamaged region. As a result, a thick residual oxide film is formed on the bottom and the lower sidewall portion of the trenchwithout causing any bird's beak.Type: GrantFiled: December 30, 2005Date of Patent: July 7, 2009Assignee: Fuji Electric Device Technology Co., Ltd.Inventors: Kazuo Shimoyama, Mutsumi Kitamura, Hongfei Lu
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Patent number: 7135387Abstract: A method for stably activating pn-successive layers in a semiconductor element in a short time is disclosed. Pulsed beams, each of which has a pulse shape that is approximately rectangular, are projected from respective laser irradiation devices and successively combined into a pulsed beam equivalent to one pulse, with which the doped layer region is irradiated. By successively projecting the pulsed beams onto the doped layer region in this way, an effect is obtained which is the same as that of irradiating the doped layer region with a single pulsed beam having a long full-width at half maximum. A high activation ratio from a shallow region to a deep region of the doped layer region is enabled. This can stably activate the semiconductor element having the pn-successive layers as the doped layer region in a short time, making possible the manufacture of semiconductor elements having superior device characteristics.Type: GrantFiled: June 24, 2004Date of Patent: November 14, 2006Assignee: Fuji Electric Device Technology Co., Ltd.Inventors: Haruo Nakazawa, Mitsuaki Kirisawa, Kazuo Shimoyama
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Publication number: 20060249797Abstract: On the top surface of a thin semiconductor wafer, top surface structures forming a semiconductor chip are formed. The top surface of the wafer is affixed to a supporting substrate with a double-sided adhesive tape. Then, from the bottom surface of the thin semiconductor wafer, a trench, which becomes a scribing line, is formed by wet anisotropic etching so that side walls of the trench are exposed. On the side walls of the trench with the crystal face exposed, an isolation layer with a conductivity type different from that of the semiconductor wafer for holding a reverse breakdown voltage is formed simultaneously with a collector region of the bottom surface diffused layer by ion implantation, followed by annealing with laser irradiation. The side walls form a substantially V-shaped or trapezoidal-shaped cross section, with an angle of the side wall relative to the supporting substrate being 30-70°. The double-sided adhesive tape is then removed from the top surface to produce semiconductor chips.Type: ApplicationFiled: March 27, 2006Publication date: November 9, 2006Applicant: FUJI ELECTRIC HOLDING CO., LTD.Inventors: Haruo Nakazawa, Kazuo Shimoyama, Manabu Takei
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Publication number: 20060166419Abstract: The method for manufacturing a semiconductor device according to the invention includes forming a thick silicon oxide film uniformly in a trench. Argon ions or the like implanted obliquely into the trench to form an ion implanted damaged region selectively in the portion of the silicon oxide film on the trench sidewall utilizing the shadowing effects of the oblique ion implantation. The silicon oxide film is wet etched to selectively remove the silicon oxide film in the ion implanted damaged region utilizing the etching rate difference, wherein the etching rate is faster in the damaged region than in the undamaged region. As a result, a thick residual oxide film is formed on the bottom and the lower sidewall portion of the trenchwithout causing any bird's beak.Type: ApplicationFiled: December 30, 2005Publication date: July 27, 2006Inventors: Kazuo Shimoyama, Mutsumi Kitamura, Hongfei Lu
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Publication number: 20060038206Abstract: A thin semiconductor wafer, on which a top surface structure and a bottom surface structure that form a semiconductor chip are formed, is affixed to a supporting substrate by a double-sided adhesive tape. Then, on the thin semiconductor wafer, a trench to become a scribing line is formed by wet anisotropic etching with a crystal face exposed so as to form a side wall of the trench. On the side wall of the trench with the crystal face thus exposed, an isolation layer for holding a reverse breakdown voltage is formed by ion implantation and low temperature annealing or laser annealing so as to be extended to the top surface side while being in contact with a p collector region as a bottom surface diffused layer. Then, laser dicing is carried out to neatly dice a collector electrode, formed on the p collector region, together with the p collector region, without presenting any excessive portions and any insufficient portions under the isolation layer.Type: ApplicationFiled: August 19, 2005Publication date: February 23, 2006Applicant: Fuji Electric Holdings Co., Ltd.Inventors: Kazuo Shimoyama, Manabu Takei, Haruo Nakazawa
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Publication number: 20050059263Abstract: A method for stably activating pn-successive layers in a semiconductor element in a short time is disclosed. Pulsed beams, each of which has a pulse shape that is approximately rectangular, are projected from respective laser irradiation devices and successively combined into a pulsed beam equivalent to one pulse, with which the doped layer region is irradiated. By successively projecting the pulsed beams onto the doped layer region in this way, an effect is obtained which is the same as that of irradiating the doped layer region with a single pulsed beam having a long full-width at half maximum. A high activation ratio from a shallow region to a deep region of the doped layer region is enabled. This can stably activate the semiconductor element having the pn-successive layers as the doped layer region in a short time, making possible the manufacture of semiconductor elements having superior device characteristics.Type: ApplicationFiled: June 24, 2004Publication date: March 17, 2005Inventors: Haruo Nakazawa, Mitsuaki Kirisawa, Kazuo Shimoyama