Patents by Inventor Kazuo Taguchi

Kazuo Taguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8454766
    Abstract: An extruded material of a free-cutting aluminum alloy excellent in embrittlement resistance at a high temperature, containing from 3 to 6% by mass of Cu and from 0.9 to 3% by mass of Bi with the balance being Aluminum and inevitable impurities, wherein a temperature for reducing the Charpy impact test value to half of the value at room temperature is 180° C. or more.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: June 4, 2013
    Assignee: Furukawa-Sky Aluminum Corp.
    Inventors: Kensuke Mori, Kazuo Taguchi
  • Patent number: 8040728
    Abstract: A semiconductor integrated circuit includes a non-volatile memory built into the semiconductor integrated circuit, the non-volatile memory electrically writing and erasing data and including a memory cell, the memory cell including: a selecting transistor controlled by a word line; an impurity diffused region formed inside a semiconductor substrate, the impurity diffused region being coupled to one of a source and a drain of the selecting transistor; a first electrode formed above the semiconductor substrate with an insulating film therebetween, the first electrode receiving a control signal and part of the first electrode having an opening; a second electrode formed above the first electrode so as to oppose the first electrode with an insulating film therebetween, the second electrode having a protrusion which opposes the impurity diffused region with a tunnel film therebetween and projects toward the semiconductor substrate through the opening of the first electrode, and storing information based on an appl
    Type: Grant
    Filed: May 20, 2009
    Date of Patent: October 18, 2011
    Assignee: Seiko Epson Corporation
    Inventor: Kazuo Taguchi
  • Publication number: 20090310417
    Abstract: A semiconductor integrated circuit includes a non-volatile memory built into the semiconductor integrated circuit, the non-volatile memory electrically writing and erasing data and including a memory cell, the memory cell including: a selecting transistor controlled by a word line; an impurity diffused region formed inside a semiconductor substrate, the impurity diffused region being coupled to one of a source and a drain of the selecting transistor; a first electrode formed above the semiconductor substrate with an insulating film therebetween, the first electrode receiving a control signal and part of the first electrode having an opening; a second electrode formed avobe the first electrode so as to oppose the first electrode with an insulating film therebetween, the second electrode having a protrusion which opposes the impurity diffused region with a tunnel film therebetween and projects toward the semiconductor substrate through the opening of the first electrode, and storing information based on an appl
    Type: Application
    Filed: May 20, 2009
    Publication date: December 17, 2009
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Kazuo TAGUCHI
  • Publication number: 20080187456
    Abstract: An extruded material of a free-cutting aluminum alloy excellent in embrittlement resistance at a high temperature, containing from 3 to 6% by mass of Cu and from 0.9 to 3% by mass of Bi with the balance being Aluminum and inevitable impurities, wherein a temperature for reducing the Charpy impact test value to half of the value at room temperature is 180° C. or more.
    Type: Application
    Filed: March 31, 2008
    Publication date: August 7, 2008
    Applicant: FURUKAWA-SKY ALUMINUM CORP.
    Inventors: Kensuke Mori, Kazuo TAGUCHI
  • Patent number: 7319627
    Abstract: A sense amplifier circuit for a non-volatile semiconductor memory device is used to output data written in a selected non-volatile memory cell and is constructed as a current mirror circuit including a first mirror transistor and a second mirror transistor of a mirror circuit. A selection gate transistor and a detection transistor of the selected non-volatile memory cell are included as part of a load circuit connected to a drain electrode of the second mirror transistor. The detection transistor has a drain electrode linked to a source electrode of the selection gate transistor. An operating current of the selection gate transistor is smaller than an operating current of the detection transistor, and an electric current output from the second mirror transistor is determined by the operating current of the selection gate transistor. This arrangement enables determination of the stable operating current of the memory cell irrespective of the state of a floating gate of the detection transistor.
    Type: Grant
    Filed: June 7, 2006
    Date of Patent: January 15, 2008
    Assignee: Seiko Epson Corporation
    Inventor: Kazuo Taguchi
  • Patent number: 7279749
    Abstract: Aspects of the invention can provide a semiconductor device and a semiconductor memory using the semiconductor device having a gate shape by which the width of the gate can be realized as designed even if relative shifts occur between the masks for forming the field regions and the gate patterns. The semiconductor device can include, in field regions, a gate (an H-type gate), a gate insulating film right under the gate, a body region right under the gate insulating film, and source/drain regions formed on both sides of and across the body region. The H-type gate can have a first section extending along the channel width direction on the field region, and a pair of second sections formed on both ends of the first section in the channel width direction and extending along the channel length direction, and is formed to be an H shape in plan view.
    Type: Grant
    Filed: August 25, 2004
    Date of Patent: October 9, 2007
    Assignee: Seiko Epson Corporation
    Inventor: Kazuo Taguchi
  • Patent number: 7262993
    Abstract: A nonvolatile semiconductor memory device including: a first capacitor, one end of the first capacitor being connected to a floating node; a detection transistor, a gate electrode of the detection transistor being connected to the floating node; a second capacitor, one end of the second capacitor being connected to the floating node, and the other end of the second capacitor being connected to a drain of the detection transistor; and an auxiliary capacitor, one end of the auxiliary capacitor being connected to the floating node, wherein, at least during write operation, a control gate voltage is supplied to the other end of the first capacitor, a control drain voltage is supplied to the other end of the second capacitor, and a capacitance ratio correction voltage which is higher than a voltage of the floating node is supplied to the other end of the auxiliary capacitor.
    Type: Grant
    Filed: March 23, 2006
    Date of Patent: August 28, 2007
    Assignee: Seiko Epson Corporation
    Inventor: Kazuo Taguchi
  • Patent number: 7211555
    Abstract: A process for efficiently preparing fine zeolite particles comprising synthesizing zeolite in the presence of an alkaline earth metal-containing compound and/or with controlling the preparation process of zeolite, thereby giving fine zeolite particles being composed of crystalline aluminosilicate, the fine zeolite particles having a fine average primary particle size, being excellent in the cationic exchange properties and the oil-absorbing ability, having a fine average aggregate particle size, and being excellent in the dispersibility; fine zeolite particles obtainable by the above process; and a detergent composition comprising the fine zeolite particles, the detergent composition being excellent in the detergency.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: May 1, 2007
    Assignee: Kao Corporation
    Inventors: Kazuo Oki, Hiroji Hosokawa, Mikio Sakaguchi, Hiroshi Kitagaito, Kazuo Taguchi, Hitoshi Takaya
  • Publication number: 20060285407
    Abstract: A sense amplifier circuit for a non-volatile semiconductor memory device is used to output data written in a selected non-volatile memory cell and is constructed as a current mirror circuit including a first mirror transistor and a second mirror transistor of a mirror circuit. A selection gate transistor and a detection transistor of the selected non-volatile memory cell are included as part of a load circuit connected to a drain electrode of the second mirror transistor. The detection transistor has a drain electrode linked to a source electrode of the selection gate transistor. An operating current of the selection gate transistor is smaller than an operating current of the detection transistor, and an electric current output from the second mirror transistor is determined by the operating current of the selection gate transistor. This arrangement enables determination of the stable operating current of the memory cell irrespective of the state of a floating gate of the detection transistor.
    Type: Application
    Filed: June 7, 2006
    Publication date: December 21, 2006
    Inventor: Kazuo Taguchi
  • Publication number: 20060221668
    Abstract: A nonvolatile semiconductor memory device including: a first capacitor, one end of the first capacitor being connected to a floating node; a detection transistor, a gate electrode of the detection transistor being connected to the floating node; a second capacitor, one end of the second capacitor being connected to the floating node, and the other end of the second capacitor being connected to a drain of the detection transistor; and an auxiliary capacitor, one end of the auxiliary capacitor being connected to the floating node, wherein, at least during write operation, a control gate voltage is supplied to the other end of the first capacitor, a control drain voltage is supplied to the other end of the second capacitor, and a capacitance ratio correction voltage which is higher than a voltage of the floating node is supplied to the other end of the auxiliary capacitor.
    Type: Application
    Filed: March 23, 2006
    Publication date: October 5, 2006
    Inventor: Kazuo Taguchi
  • Patent number: 7098698
    Abstract: To provide a semiconductor integrated circuit device and a sense amplifier in a memory in which a transistor element whose body potential is variable is built in an appropriate location and which can produce high speed operation with a layout advantage, an SOI transistor integrated circuit, each source of p-channel MOS transistor Qp1 and Qp2 is given a high potential level Vdd, for example, a supply-power potential, and respective body potentials are set as variable potentials corresponding to mutually inverse signal inputs Vin and Bvin, and a control signal CS is given to each gate. Also, each source and body of n-channel MOS transistor Qn1 and Qn2 are given a low potential level Vsa, for example, an earth potential, the signal inputs Vin and Bvin are supplied to respective gates. A connection node of these drains of the transistors Qp1 and Qn1 is connected to a signal output section Vout. Also, a connection node of the drains of the transistors Qp2 and Qn2 is connected to a signal output section BVout.
    Type: Grant
    Filed: August 12, 2004
    Date of Patent: August 29, 2006
    Assignee: Seiko Epson Corporation
    Inventor: Kazuo Taguchi
  • Patent number: 6962632
    Abstract: Disclosed are aluminum alloy hollow materials and processes for producing the same wherein an aluminum alloy hollow material is produced by subjecting an ingot of an aluminum alloy containing 0.3˜1.5 wt % Mn to port hole extrusion or port hole extrusion and drawing-elongation processing and wherein a difference in electric conductivity between individual portions in lengthwise direction of the hollow material is not more than 1.0 IACS %. According to the aluminum alloy hollow materials, preferential corrosion in welding potions in port hole extrusion can be prevented.
    Type: Grant
    Filed: February 4, 2004
    Date of Patent: November 8, 2005
    Assignee: Furukawa-Sky Aluminum Corp.
    Inventors: Kazuo Taguchi, Toshio Ohta
  • Patent number: 6908520
    Abstract: Disclosed are aluminum alloy hollow materials and processes for producing the same wherein an aluminum alloy hollow material is produced by subjecting an ingot of an aluminum alloy containing 0.3˜1.5 wt % Mn to port hole extrusion or port hole extrusion and drawing-elongation processing and wherein a difference in electric conductivity between individual portions in lengthwise direction of the hollow material is not more than 1.0 IACS %. According to the aluminum alloy hollow materials, preferential corrosion in welding potions in port hole extrusion can be prevented.
    Type: Grant
    Filed: January 26, 2001
    Date of Patent: June 21, 2005
    Assignee: The Furukawa Electric Co., Ltd.
    Inventors: Kazuo Taguchi, Toshio Ohta
  • Publication number: 20050082613
    Abstract: Aspects of the invention can provide a semiconductor device including a transistor having a gate shape, which enables a source area and a body contact area to be connected without using wiring and with no gate part protruding to the source area side, and a semiconductor memory. The semiconductor device can have field regions, a transistor which includes a gate (L type gate), a gate insulating film directly below the gate, a body area directly below the gate insulating film, and a source area and a drain area formed on both sides which hold the body area in between. The gate can consist essentially of a first part extending along a channel width direction on the field region and a second part protruding from one end of the first part in the channel width direction to the drain side, and being formed in the L type gate in a plan view.
    Type: Application
    Filed: August 13, 2004
    Publication date: April 21, 2005
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Kazuo Taguchi
  • Publication number: 20050082612
    Abstract: To provide a semiconductor integrated circuit device and a sense amplifier in a memory in which a transistor element whose body potential is variable is built in an appropriate location and which can produce high speed operation with a layout advantage, an SOI transistor integrated circuit, each source of p-channel MOS transistor Qp1 and Qp2 is given a high potential level Vdd, for example, a supply-power potential, and respective body potentials are set as variable potentials corresponding to mutually inverse signal inputs Vin and Bvin, and a control signal CS is given to each gate. Also, each source and body of n-channel MOS transistor Qn1 and Qn2 are given a low potential level Vsa, for example, an earth potential, the signal inputs Vin and Bvin are supplied to respective gates. A connection node of these drains of the transistors Qp1 and Qn1 is connected to a signal output section Vout. Also, a connection node of the drains of the transistors Qp2 and Qn2 is connected to a signal output section BVout.
    Type: Application
    Filed: August 12, 2004
    Publication date: April 21, 2005
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Kazuo Taguchi
  • Publication number: 20050077576
    Abstract: Aspects of the invention can provide a semiconductor device and a semiconductor memory using the semiconductor device having a gate shape by which the width of the gate can be realized as designed even if relative shifts occur between the masks for forming the field regions and the gate patterns. The semiconductor device can include, in field regions, a gate (an H-type gate), a gate insulating film right under the gate, a body region right under the gate insulating film, and source/drain regions formed on both sides of and across the body region. The H-type gate can have a first section extending along the channel width direction on the field region, and a pair of second sections formed on both ends of the first section in the channel width direction and extending along the channel length direction, and is formed to be an H shape in plan view.
    Type: Application
    Filed: August 25, 2004
    Publication date: April 14, 2005
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Kazuo Taguchi
  • Publication number: 20050079994
    Abstract: A process for efficiently preparing fine zeolite particles comprising synthesizing zeolite in the presence of an alkaline earth metal-containing compound and/or with controlling the preparation process of zeolite, thereby giving fine zeolite particles being composed of crystalline aluminosilicate, the fine zeolite particles having a fine average primary particle size, being excellent in the cationic exchange properties and the oil-absorbing ability, having a fine average aggregate particle size, and being excellent in the dispersibility; fine zeolite particles obtainable by the above process; and a detergent composition comprising the fine zeolite particles, the detergent composition being excellent in the detergency.
    Type: Application
    Filed: September 30, 2004
    Publication date: April 14, 2005
    Applicant: KAO CORPORATION
    Inventors: Kazuo Oki, Hiroji Hosokawa, Mikio Sakaguchi, Hiroshi Kitagaito, Kazuo Taguchi, Hitoshi Takaya
  • Patent number: 6831056
    Abstract: A process for efficiently preparing fine zeolite particles comprising synthesizing zeolite in the presence of an alkaline earth metal-containing compound and/or with controlling the preparation process of zeolite, thereby giving fine zeolite particles being composed of crystalline aluminosilicate, the fine zeolite particles having a fine average primary particle size, being excellent in the cationic exchange properties and the oil-absorbing ability, having a fine average aggregate particle size, and being excellent in the dispersibility; fine zeolite particles obtainable by the above process; and a detergent composition comprising the fine zeolite particles, the detergent composition being excellent in the detergency.
    Type: Grant
    Filed: July 6, 2001
    Date of Patent: December 14, 2004
    Assignee: Kao Corporation
    Inventors: Kazuo Oki, Hiroji Hosokawa, Mikio Sakaguchi, Hiroshi Kitagaito, Kazuo Taguchi, Hitoshi Takaya
  • Publication number: 20040154709
    Abstract: Disclosed are aluminum alloy hollow materials and processes for producing the same wherein an aluminum alloy hollow material is produced by subjecting an ingot of an aluminum alloy containing 0.3˜1.5 wt % Mn to port hole extrusion or port hole extrusion and drawing-elongation processing and wherein a difference in electric conductivity between individual portions in lengthwise direction of the hollow material is not more than 1.0 IACS %. According to the aluminum alloy hollow materials, preferential corrosion in welding potions in port hole extrusion can be prevented.
    Type: Application
    Filed: February 4, 2004
    Publication date: August 12, 2004
    Inventors: Kazuo Taguchi, Toshio Ohta
  • Publication number: 20040146701
    Abstract: A semiconductor substrate, method and device are provided. The substrate is capable of securing a more stable substrate potential and that has a highly reliable SOI structure. A P− type single-crystal silicon layer for forming a device is provided on an insulating layer. In addition, under the insulating layer a P-type support substrate is formed, for example. This support substrate is provided in advance with N-type well patterns. These are deposited as multi-layers so as to comprise a semiconductor substrate having an SOI structure. A predetermined electric potential is applied to each of the well patterns via a connection member that passes through the insulating layer. For example, since a pad is provided in the peripheral region of a chip, regions provided with the well patterns are made to correspond to the pad. Other regions are also provided in accordance with device regions.
    Type: Application
    Filed: November 24, 2003
    Publication date: July 29, 2004
    Inventor: Kazuo Taguchi