Patents by Inventor Kazuo Taniguchi

Kazuo Taniguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8314468
    Abstract: A silicon drift detector (SDD) comprising electrically isolated rings. The rings can be individually biased doped rings. One embodiment includes an SDD with a single doped ring. Some of the doped rings may not require a bias voltage. Some of the rings can be field plate rings. The field plate rings may all use the same biasing voltage as a single outer doped ring. The ring widths can vary such that the outermost ring is widest and the ring widths decrease with each subsequent ring towards the anode.
    Type: Grant
    Filed: November 12, 2009
    Date of Patent: November 20, 2012
    Assignee: Moxtek, Inc.
    Inventors: Derek Hullinger, Hideharu Matsuura, Kazuo Taniguchi, Tadashi Utaka
  • Publication number: 20100314706
    Abstract: A silicon drift detector (SDD) comprising electrically isolated rings. The rings can be individually biased doped rings. One embodiment includes an SDD with a single doped ring. Some of the doped rings may not require a bias voltage. Some of the rings can be field plate rings. The field plate rings may all use the same biasing voltage as a single outer doped ring. The ring widths can vary such that the outermost ring is widest and the ring widths decrease with each subsequent ring towards the anode.
    Type: Application
    Filed: November 12, 2009
    Publication date: December 16, 2010
    Inventors: Derek Hullinger, Hideharu Matsuura, Kazuo Taniguchi, Tadashi Utaka
  • Patent number: 7536516
    Abstract: A shared memory device capable of simplifying wiring to a memory, preventing a decline of performance due to an increase of the area and long wiring, and improving extensibility of scalability of the system is provided: wherein the device has a plurality of memory systems each including a memory macro, a processor, and a memory control unit for controlling an access to a memory macro; wherein the memory control unit of each of the memory systems transfers information between the processor and memory macro and transfers information with a memory control unit of a different memory system; the memory macro of each of the memory systems has a memory interface capable of transferring data; and the memory interfaces of the memory macros of different memory systems are mutually connected.
    Type: Grant
    Filed: February 1, 2006
    Date of Patent: May 19, 2009
    Assignee: Sony Corporation
    Inventors: Goragot Wongpaisarnsin, Kazuo Taniguchi, Masayuki Miyabayashi
  • Publication number: 20070123224
    Abstract: This invention is to provide a technology for preventing information from being leaked from a mobile phone. For this purpose, this invention includes: receiving a request for data to select a calling destination from a first mobile phone capable of executing voice communication and data communication; identifying calling destination candidates registered in a data storage in association with a user of the first mobile phone by identification information other than telephone numbers of the calling destination candidates; and transmitting data to specify and select anyone of the identified calling destination candidates by the identification information other than the telephone numbers of the calling destination candidates, to the first mobile phone. Because the telephone number of the client is not sent to the mobile phone, the leakage of the client information is prevented, even if the mobile phone is stolen.
    Type: Application
    Filed: January 25, 2006
    Publication date: May 31, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Soichi Nishiyama, Yoshiyuki Itoh, Yu Minakuchi, Yasuhiko Awamoto, Naoto Matsudaira, Fumio Horie, Yusuke Tohnai, Minoru Takezawa, Kazuo Taniguchi, Hiroshi Nezu
  • Publication number: 20060179256
    Abstract: A shared memory device capable of simplifying wiring to a memory, preventing a decline of performance due to an increase of the area and long wiring, and improving extensibility of scalability of the system is provided: wherein the device has a plurality of memory systems each including a memory macro, a processor, and a memory control unit for controlling an access to a memory macro; wherein the memory control unit of each of the memory systems transfers information between the processor and memory macro and transfers information with a memory control unit of a different memory system; the memory macro of each of the memory systems has a memory interface capable of transferring data; and the memory interfaces of the memory macros of different memory systems are mutually connected.
    Type: Application
    Filed: February 1, 2006
    Publication date: August 10, 2006
    Applicant: Sony Corporation
    Inventors: Goragot Wongpaisarnsin, Kazuo Taniguchi, Masayuki Miyabayashi
  • Patent number: 6745302
    Abstract: A semiconductor memory enabling a read modify write operation of data, comprising: a memory cell array including a plurality of memory cells arranged in a matrix and able to be written with and read out data; a read address decoding means for independently decoding an address of a read memory cell in response to a read address; a write address decoding means for independently decoding an address of a write memory cell in response to a write address; a data reading means for reading data of a memory cell addressed by the read address decoding means; a data writing means for writing data to a memory cell addressed by the write address decoding means; and an address delay means by which a write address decoded by the write address decoding means is delayed by a predetermined time from a read address decoded by the read address decoding means, wherein the predetermined time is set as a predetermined plurality of times of basic synchronization pulse periods so that the data read modify write operation is accomplis
    Type: Grant
    Filed: September 13, 1999
    Date of Patent: June 1, 2004
    Assignee: Sony Corporation
    Inventors: Kazuo Taniguchi, Masaharu Yoshimori
  • Patent number: 6134161
    Abstract: A logic IC including an embedded memory is provided with a test circuit therein which allows the embedded memory to be tested by using only three additional external pins of the logic IC for test purposes without regard to the bit count of a unit in which data is written into or read out from the embedded memory. In addition, the embedded memory can be tested by adopting a method that requires a period of testing time shorter than the related art one.
    Type: Grant
    Filed: October 1, 1997
    Date of Patent: October 17, 2000
    Assignee: Sony Corporation
    Inventors: Kazuo Taniguchi, Atsushi Tamura, Ken Matsumoto
  • Patent number: 6040844
    Abstract: A system for mapping texture data at high speed with flexibility to different applications wherein texture data is sent to a memory interface (MEMIF) thorough a digital differential analyzer (DDA) and a texture mapping unit (TMAP) and loaded to free areas of a Z coordinatory memory (ZBUF) and a drawing data memory (FBUF). A Z coordinate value or drawing data is read/written through a bidirectional port. The TMAP converts texture coordinates into a physical address, reads texture data from dedicated read ports of the ZBUF and the FBUF with the physical address, and maps the texture data. Each of the ZBUF and the FBUF has a DRAM unit and an auxiliary memory. Data of one row of the DRAM unit can be sent to the auxiliary memory means at a time. When desired texture data is not present in the auxiliary memory, data of the entire row of the desired texture data is sent to the auxiliary memory and then read.
    Type: Grant
    Filed: July 24, 1997
    Date of Patent: March 21, 2000
    Assignee: Sony Corporation
    Inventors: Yuji Yamaguchi, Masaharu Yoshimori, Hiroyuki Ozawa, Ryohei Iida, Kazuo Taniguchi
  • Patent number: 5996052
    Abstract: A semiconductor memory enabling a read modify write operation of data, comprising: a memory cell array including a plurality of memory cells arranged in a matrix and able to be written with and read out data; a read address decoding means for independently decoding an address of a read memory cell in response to a read address; a write address decoding means for independently decoding an address of a write memory cell in response to a write address; a data reading means for reading data of a memory cell addressed by the read address decoding means; a data writing means for writing data to a memory cell addressed by the write address decoding means; and an address delay means by which a write address decoded by the write address decoding means is delayed by a predetermined time from a read address decoded by the read address decoding means, wherein the predetermined time is set as a predetermined plurality of times of basic synchronization pulse periods so that the data read modify write operation is accomplis
    Type: Grant
    Filed: August 4, 1997
    Date of Patent: November 30, 1999
    Assignee: Sony Corporation
    Inventors: Kazuo Taniguchi, Masaharu Yoshimori
  • Patent number: 5818765
    Abstract: A semiconductor memory comprising a memory cell array including a plurality of the memory cells arranged in a matrix, the memory cells being able to be written with and read out data; a reading/writing means for reading and writing data with respect to a selected memory cell; a plurality of auxiliary data storing means arranged in series, a first means among them being connected to the memory cell array and each of the auxiliary data storing means storing a part of the data stored in the memory cell array; a plurality of data output means, each of the data output means being connected to one of the auxiliary data storing means; and a plurality of external data buses, each of the external data buses being connected to one of the data output means; each of the data output means being able to independently output the data stored in a corresponding auxiliary data storing means to a corresponding external data bus.
    Type: Grant
    Filed: August 18, 1997
    Date of Patent: October 6, 1998
    Assignee: Sony Corporation
    Inventors: Kazuo Taniguchi, Masayuki Miyabayashi, Yuji Yamaguchi
  • Patent number: 5403454
    Abstract: A heat-shrinkable polyester tube, which is a tube having heat shrinkability imparted by subjecting an unstretched tube made of a thermoplastic polyester resin to tubular stretching, and which has a crystallinity of not higher than 20% and a shrinkage of more than 5% and not more than 26% in the longitudinal direction (MD) and a shrinkage of at least 25% in the radial direction (TD).
    Type: Grant
    Filed: July 18, 1994
    Date of Patent: April 4, 1995
    Assignee: Mitsubishi Plastics Industries Limited
    Inventors: Kazuo Taniguchi, Tetsuo Murakami
  • Patent number: 5368811
    Abstract: A heat-shrinkable polyester tube, which is a tube having heat shrinkability imparted by subjecting an unstretched tube made of a thermoplastic polyester resin to tubular stretching, and which has a crystallinity of not higher than 20% and a shrinkage of more than 5% and not more than 26% in the longitudinal direction (MD) and a shrinkage of at least 25% in the radial direction (TD).
    Type: Grant
    Filed: February 12, 1993
    Date of Patent: November 29, 1994
    Assignee: Mitsubishi Plastics Industries Limited
    Inventors: Kazuo Taniguchi, Tetsuo Murakami
  • Patent number: 5059671
    Abstract: This invention relates to a process for manufacturing a spray urethane elastomer. More particularly it relates to a process for manufacturing a solventless, non-cellular spray urethane elastomer, which comprises spraying a partial prepolymer component having a high molar ratio of NCO/OH prepared from an organic polyisocyanate and from polytetramethylene ether glycol (PTMEG) having a molecular weight of 400 to 2000 and a resin component containing the PTMEG, a specified chain extender and an organobismuth compound catalyst onto a substrate by use of a two components high pressure spray machine.According to the present invention, spraying only of the stock solutions by use of the two components high pressure spray machine accomplishes coating and the stock solutions are cured in one second to ten and several seconds after being sprayed without producing cells even when thick-coated.
    Type: Grant
    Filed: December 21, 1989
    Date of Patent: October 22, 1991
    Assignee: Mitsui Toatsu Chemicals, Inc.
    Inventors: Kazuo Taniguchi, Kazuhiro Imaoka, Tetsuyoshi Ogura, Hiroaki Sakaguchi
  • Patent number: 4164655
    Abstract: An apparatus for measuring the quantity of asphalt ingredient in an asphalt compound in an apparatus for mixing asphalt ingredient and an aggregate to form the asphalt compound including a neutronic line which reacts with a hydrogen atom of the asphalt ingredient in such a manner as to decrease the energy in the neutronic line so as to detect the quantity of asphalt ingredient in the asphalt compound, a continuous conveying means for supplying asphalt compound to the neutronic line and a means responsive to the neutronic line for automatically adjusting the amount of asphalt ingredient in the asphalt compound whereby the amount of asphalt ingredient in the asphalt compound is maintained at a standard value.
    Type: Grant
    Filed: December 30, 1977
    Date of Patent: August 14, 1979
    Assignee: Noma Komuten Company Limited
    Inventors: Ichiro Noma, Kazuo Taniguchi