Patents by Inventor Kazuo Tanimoto

Kazuo Tanimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory circuit having a decoder
    Patent number: 4470133
    Abstract: A memory circuit has a decoder circuit for receiving address signals and generating word designating signals. The decoder circuit has a plurality of decoder circuit blocks and includes a circuit for receiving some of the address signals and generating signals designating one of the decoder circuit blocks, whereby the current flowing in each of the decoder circuit blocks is reduced as long as the blocks are not designated.
    Type: Grant
    Filed: December 16, 1981
    Date of Patent: September 4, 1984
    Assignee: Fujitsu Limited
    Inventor: Kazuo Tanimoto
  • Static memory circuit
    Patent number: 4409679
    Abstract: A static memory circuit incorporating memory cells of a MOS static type comprising a plurality of potential setting circuits for setting the ground side potential of one selected memory cell to be lower than those of other non-selected memory cells. Thus, reducing power dissipation by reducing current flowing through half-selected and non-selected memory cells without reducing read speed.
    Type: Grant
    Filed: March 26, 1981
    Date of Patent: October 11, 1983
    Assignee: Fujitsu Limited
    Inventors: Setsuo Kurafuji, Kazuo Tanimoto