Patents by Inventor Kazuo Terada

Kazuo Terada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5760452
    Abstract: Disclosed are an improved semiconductor memory cell suitable for high integration and a novel method of fabricating the same. The memory cell has a large capacitance and a small area. The memory cell also has a plurality of bit-lines buried in an isolation region in a semiconductor substrate. The bit-line has a very small width and thickness thereby reducing a parasitic capacity between the bit-line and the semiconductor substrate. The memory cell may further be provided with a noise shielding line. Further, disclosed is a novel memory cell array of a semiconductor memory. The buried bit-line is coupled with a bit-line connecting sub-arrays and both are separated by a insulation film. A plurality of pairs of the bit-lines are arranged in rows. A word-line is coupled with a sub-word line and both are separated by a insulation film. A plurality of pairs of the word-lines are arranged in columns. The memory cells are arranged at the intersections of the buried bit-lines and the word-lines.
    Type: Grant
    Filed: October 15, 1996
    Date of Patent: June 2, 1998
    Assignee: NEC Corporation
    Inventor: Kazuo Terada
  • Patent number: 5616264
    Abstract: A temperature control method in a rapid heat treatment apparatus comprising simulatively heating dummy wafers in a process tube and previously detecting and grasping by temperature sensors a wafer temperature rising pattern, a heater temperature rising pattern and an internal atmosphere temperature rising pattern, arranging wafers to be processed in the process tube, detecting a temperature of each zone and that of each heater element by the temperature sensors, upon heating the wafers, and controlling each heater element on the basis of the detected temperatures and the wafer, heater and internal atmosphere temperature rising patterns by a controller to rapidly and uniformly raise the temperature of each wafer until the temperature of the wafers in each zone reaches the intended one and becomes stable.
    Type: Grant
    Filed: June 13, 1994
    Date of Patent: April 1, 1997
    Assignees: Tokyo Electron Limited, Tokyo Electron Tohoku Limited
    Inventors: Katsuo Nishi, Kazuo Terada, Wataru Ohkase, Kenichi Yamaga
  • Patent number: 5334257
    Abstract: A plurality of ring trays supporting loaded treatment objects are arranged in parallel at predetermined spacing in the vertical axis direction and are supported by rods at a minimum of three locations separated from the rod couplings. Cutouts are provided in each ring tray that do not extend to the ring tray center open area. Supporting teeth are provided on the arms driven by drive devices and are inserted via the cutouts. The supporting teeth straddle the ring tray and are shifted relatively on both sides of the vertical direction, and can exchange the wafers between the ring tray and the supporting teeth. By this, problems occurring with regard to various types of heat treatment of the treatment objects, such as treatment object slippage, can be prevented. In addition, a plurality of treatment objects can be exchanged at one time, thereby allowing the exchanging time to be shortened.
    Type: Grant
    Filed: May 25, 1993
    Date of Patent: August 2, 1994
    Assignees: Tokyo Electron Kabushiki Kaisha, Tokyo Electron Tohoku Kab. Kaisha
    Inventors: Hironobu Nishi, Kazuo Terada
  • Patent number: 5324540
    Abstract: A system for supporting and rotating substrates in a process chamber comprising a first exhaust vacuum pump for exhausting the process chamber, a shaft vertically extending into the process chamber to support wafers in it, bearings for supporting the shaft rotatable, a mechanism for rotating the shaft together with the wafers, a bearing casing for covering the bearings and communicated with the process chamber, a second exhaust vacuum pump for exhausting the bearing casing, and a controller for controlling the first and second exhaust vacuum pumps in such a way that the bearing casing is exhausted by the second exhaust vacuum pump before the process chamber is exhausted by the first exhaust vacuum pump.
    Type: Grant
    Filed: August 17, 1993
    Date of Patent: June 28, 1994
    Assignees: Tokyo Electron Limited, Tokyo Electron Tohoku Limited
    Inventor: Kazuo Terada
  • Patent number: 5061412
    Abstract: An iron ore or mill scale is crushed to form a powder having an average particle diameter not exceeding 12 microns. The powder is heated at a temperature of 600.degree. C. to 900.degree. C. in the presence of oxygen to form an iron oxide containing at least 98.0% of Fe.sub.2 O.sub.3. The iron oxide is mixed with strontium oxide or carbonate. The mixture is calcined to form strontium ferrite. The calcined product is pulverized, the crushed material is molded in a magnetic field, and the molded product is sintered to yield a magnet of strontium ferrite having a high level of performance.
    Type: Grant
    Filed: March 30, 1990
    Date of Patent: October 29, 1991
    Assignee: Sumitomo Special Metal Co. Ltd.
    Inventors: Kunio Okumori, Kazuo Terada
  • Patent number: 5053156
    Abstract: A process for producing ferrite powder for high performance ferrite magnets is claimed, which comprises: milling magnetite or mill scale into a powder comprising particles of specified particle size; oxidizing the milled product to obtain a powder containing 98.0% or higher Fe.sub.2 O.sub.3 ; further adding thereto iron oxide originated from iron chloride or iron sulfide together with an oxide or a carbonate of Sr or Ba; and calcining the resulting powder mixture.The present invention provides a low-cost process for producing ferrite powder for ferrite magnets having high pellet strength as well as high magnetic properties, from which a high performance Sr-ferrite magnet as well as Ba-ferrite magnet suitable for use in automobile motors can be readily produced by simply molding the powder under a magnetic field and sintering.
    Type: Grant
    Filed: November 28, 1990
    Date of Patent: October 1, 1991
    Assignee: Sumitomo Special Metals Co. Ltd.
    Inventors: Kunio Okumori, Kazuo Terada
  • Patent number: 4706107
    Abstract: A semiconductor memory device has a semiconductor substrate with a first semiconductor region of one conductivity type in the substrate. A second semiconductor region of the opposite conductivity type is formed in the first semiconductor region. A third semiconductor region of the opposite conductivity type is arranged to be in contact with the first semiconductor region. A fourth semiconductor region of the one conductivity type is formed in the third semiconductor region. A fifth semiconductor region of the one conductivity type, within the semiconductor substrate, has a concentration which is higher than the impurity concentration of the first semiconductor region and is provided under the third semiconductor region. A continuous gate electrode is provided via a gate insulating layer formed on the surface of the first semiconductor region and on the surface of the third semiconductor region.
    Type: Grant
    Filed: February 20, 1986
    Date of Patent: November 10, 1987
    Assignee: Nippon Electric Co., Ltd.
    Inventors: Kazuo Terada, Susumu Kurosawa, Shunichi Suzuki